Patents by Inventor Vinoth Kumar

Vinoth Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982290
    Abstract: A blower of an HVAC system includes an air inlet, an air outlet, a blower wheel with blades, a motor operable to cause the blower wheel to rotate, and a blower housing within which the blower wheel is positioned. The blower housing includes a top panel, a bottom panel, and a connecting panel. The top panel and the bottom panel are connected to the connecting panel. The top panel includes a curved edge extending from a bottom edge of the connecting panel to a top edge of the connecting panel. An expansion angle of the curved edge of the top panel changes as a function of position along the curved edge of the top panel. The bottom panel may have a shape corresponding to a mirror image to that of the top panel.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: May 14, 2024
    Assignee: Lennox Industries Inc.
    Inventors: Patric Ananda Balan Thobias, Vinoth Kumar Settu, Prabhu Prakasam, Sangameshwaran Sadhasivam
  • Publication number: 20240146567
    Abstract: For each discovered smart socket, the smart socket is automatically added to a supervisor database and a predetermined set of two or more objects for the smart socket are automatically added to the supervisor database. One or more predetermined alarm extensions are automatically added to predetermined ones of the two or more objects of the smart socket in the supervisor database. One or more predetermined history extensions are automatically added to predetermined ones of the two or more objects of the smart socket in the supervisor database. Predetermined ones of the two or more objects and/or extensions of each of the discovered smart sockets are automatically mapped to a predetermined dashboard.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 2, 2024
    Inventors: Shyam Kumar Mohan DAS, Neil Philip BROWN, Philip Anthony BARNETT, Rajiv R. SINGH, Priyanka Vivek JOSHI, Venkatram D., Vinoth DURAIRAJ, Pooja Bhimbahadur DANGI
  • Publication number: 20240146061
    Abstract: Energy consumption may be reduced by tracking a measure of baseline energy over time in order to determine which of the one or more appliances have a power on mode and a power standby mode based at least in part on the measure of baseline energy delivered to each of the appliances during the baseline time period, wherein the power standby mode consumes less power than the power on mode. During subsequent operation, the supervisor identifies when an appliance is in a power standby mode, and turns off the socket receptacles of the smart sockets that corresponds to those appliances identified as being in their power standby mode.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 2, 2024
    Inventors: Shyam Kumar Mohan DAS, Neil Philip BROWN, Philip Anthony BARNETT, Rajiv R. SINGH, Priyanka Vivek JOSHI, Venkatram D, Vinoth DURAIRAJ
  • Publication number: 20240142502
    Abstract: A method for maintaining a measure of accumulated energy delivered to an appliance includes a supervisor repeatedly receiving from a first smart socket a measure of energy delivered to the appliance by the first smart socket and maintaining a measure of accumulated energy delivered to the appliance. When the first smart socket fails and is replaced, the method includes repeatedly receiving from the second smart socket a measure of energy delivered to the appliance by the second smart socket, maintaining the measure of accumulated energy delivered to the appliance based at least in part on the measures previously received from the first smart socket and the measures repeatedly received from the second smart socket of energy delivered to the appliance by the second smart socket, and displaying the measure of accumulated energy delivered to the appliance on a dashboard.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 2, 2024
    Inventors: Shyam Kumar Mohan DAS, Neil Philip BROWN, Philip Anthony BARNETT, Rajiv R. SINGH, Priyanka Vivek JOSHI, Venkatram D, Vinoth DURAIRAJ
  • Patent number: 11881981
    Abstract: A method includes executing, on a processor of a computing device, instructions that cause the computing device to perform operations. The operations include executing, on a processor of a computing device, instructions that cause the computing device to perform operations. The operations include receiving site features associated with a communication site and receiving event features associated with a potential outage-causing event. A classifying engine is employed to generate an impact metric indicating an effect on the communication site from the potential outage-causing event based on the site features and the event features.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: January 23, 2024
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Allie Khalil Watfa, Nilam Jyoti Sharma, Manikandan Murugesan, Rajesh Pratabrai Lalwani, Adabel Jasmin Marquina, Vinoth Kumar Rajasekar
  • Publication number: 20240022558
    Abstract: A networking device credential information reset system includes credential information reset authorization devices coupled to a networking device. At least one of the credential information reset authorization devices receives a networking device credential information reset request from the networking device and, in response, generates a networking device credential information reset alert and provides it for display on an administrator device. Following the networking device credential information reset alert being provided for display on the administrator device, a first credential information reset authorization device receives first credential information for the first credential information reset authorization device from the administrator device, validates the first credential information and, in response, provides a credential information reset authorization to the networking device that is configured to cause the networking device to reset second credential information for the networking device.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 18, 2024
    Inventors: Senthil Kumar Ganesan, Venkatesan Mahalingam, Vinoth Kumar Arumugam
  • Publication number: 20230315588
    Abstract: This document describes systems and techniques for a hardware-based save-and-restore controller in an SoC. The described systems and techniques can automatically save and restore access control configurations (e.g., register states) of IP subsystems during a power-down and a power-up sequence, respectively. The save operation is initiated by a local save-and-restore (L SAR) controller and performed by the IP subsystems writing the configuration values to a central save-and-restore (C-SAR) controller before powering down a power domain. The C-SAR controller saves the configuration information in a memory located in an always-on power domain. The described systems and techniques initiate, via the L SAR controller, a restore operation as part of the power-up sequence. In this way, the described systems and techniques provide scalable save-and-restore services, support a large number of power domains, and allow a variable number of access control configurations to be saved and restored.
    Type: Application
    Filed: September 11, 2020
    Publication date: October 5, 2023
    Applicant: Google LLC
    Inventor: Vinoth Kumar Deivasigamani
  • Patent number: 11741194
    Abstract: The present invention relates to a system and method for application debt management with zero maintenance strategy that make the applications “fit for use” and “fit for purpose”. The objective is to ensure that applications run at the lowest cost, deliver maximum performance and serve the purpose for which it was developed. The machine learning enabled debt engine of present system reads the unstructured ticket data or debts, eliminates noise, and classify the debts into one of predefined categories. This is followed by remediation of debt via either of automation or healing workbench based on predetermined priorities.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: August 29, 2023
    Assignee: COGNIZANT TECHNOLOGY SOLUTIONS INDIA PVT. LTD.
    Inventors: Srinivasan Thiagarajan, Saritha Panapparambil Abubacker, Surendranathan Ardhanari, Vinoth Kumar Devarajan, Yuvarajan Mani, Suganya Thirumalaisamy, Saranya Nedumaran, Vijayalakshmi Senthilkumar, Manikandan Namasivayam, Radha Ponram, Monalisa Behera
  • Patent number: 11736389
    Abstract: Embodiments herein facilitate the modification of data traffic load balancing on information handling systems affected by a networking information handling system having the status of one or more of its uplinks changed from operable to inoperable or from inoperable to operable. In one or more embodiments, an agent operating on or in conjunction with a networking information handling system (e.g., a TOR) detects a change in one its links. The agent sends a message to information handling system(s) (e.g., hosts) that are communicatively coupled to the TOR regarding the change in status. Based upon the TOR's message, a host may adjust its traffic load balancing to compensate for the status change. Embodiments, therefore, help efficiently utilize network pathways.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: August 22, 2023
    Assignee: DELL PRODUCTS L.P.
    Inventors: Sudharsan Dhamal Gopalarathnam, Vinoth Kumar Arumugam
  • Patent number: 11710130
    Abstract: A computer-implemented method and apparatus are provided to reduce false fraudulent declines of transactions. Payment processor (PP) systems may be provided with a request acceptor and a replacement transaction generator. The request acceptor receives a notification of a decline of a first transaction attempted by a cardholder with a merchant, for allegedly fraudulent, and a request to determine whether the first transaction was falsely identified as fraudulent, and if so, to remedy the first transaction. The replacement transaction generator generates, in response to a determination that the first transaction was falsely identified as fraudulent, and the merchant is a false fraudulent reduction partner merchant, a replacement second transaction to replace the declined first transaction. The replacement second transaction may include a bypass authorization code, and made available to the cardholder to use to transact with the merchant bypassing the declined first transaction.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: July 25, 2023
    Assignee: Visa International Service Association
    Inventors: Satish Kumar, Vinoth Kumar Kalaiselvan
  • Publication number: 20230128902
    Abstract: A blower of an HVAC system includes an air inlet, an air outlet, a blower wheel with blades, a motor operable to cause the blower wheel to rotate, and a blower housing within which the blower wheel is positioned. The blower housing includes a top panel, a bottom panel, and a connecting panel. The top panel and the bottom panel are connected to the connecting panel. The top panel includes a curved edge extending from a bottom edge of the connecting panel to a top edge of the connecting panel. An expansion angle of the curved edge of the top panel changes as a function of position along the curved edge of the top panel. The bottom panel may have a shape corresponding to a mirror image to that of the top panel.
    Type: Application
    Filed: October 21, 2021
    Publication date: April 27, 2023
    Inventors: Patric Ananda Balan Thobias, Vinoth Kumar Settu, Prabhu Prakasam, Sangameshwaran Sadhasivam
  • Publication number: 20230109396
    Abstract: Examples described herein relate to a network interface device. In some examples, packet processing circuitry in the network interface device is to receive a first packet and based on the first packet being associated with an identifier for which an entry is not present in a look-up table accessible to the packet processing circuitry, the packet processing circuitry is to provide the identifier for the first packet and an action for the identifier of the first packet and cause the first packet to configure a second look-up-table accessible to the packet processing circuitry with the action for the identifier.
    Type: Application
    Filed: October 1, 2022
    Publication date: April 6, 2023
    Inventors: Anjali Singhai JAIN, Nupur JAIN, Elazar COHEN, John Andrew FINGERHUT, Neha SINGH, Vinoth Kumar CHANDRA MOHAN, Alana SWEAT, Arunkumar BALAKRISHNAN
  • Publication number: 20230023587
    Abstract: If a secure element accesses a resource that is separate from the secure element, conducting a secure transaction can be inefficient in terms of power or time. Power usage is inefficient if the resource is never permitted to sleep, and transaction time is inefficient if the resource is permitted to sleep, and the user experiences a delay. To enable dual efficiency, a resource entity is permitted to be powered down. The resource entity is then powered up speculatively by an activation controller. The activation controller predicts an upcoming secure transaction based on sensor output, such as a position fix or a detected electromagnetic field. Based on monitored sensor output, the activation controller issues an activation signal to power up the secure element or the resource entity prior to initiation of the upcoming secure transaction. Thus, power can be conserved without introducing a transaction-processing latency.
    Type: Application
    Filed: March 12, 2020
    Publication date: January 26, 2023
    Applicant: Google LLC
    Inventors: Olivier Jean Benoit, Prasad Modali, Vinoth Kumar Deivasigamani, Benjamin K. Dodge
  • Publication number: 20230020841
    Abstract: This document describes a secure element that leverages the resources of a computer system to perform specialized functions using sensitive information. The secure element securely stores sensitive information on flash memory of the computer system. In response to a request requiring use of sensitive information, the secure element loads a security application and sensitive information from the computer system. By leveraging external resources, the secure element may flexibly accommodate increasing resource requirements of the computer system and be used in a wide range of computer systems.
    Type: Application
    Filed: February 27, 2020
    Publication date: January 19, 2023
    Applicant: Google LLC
    Inventors: Olivier Jean Benoit, Prasad Modali, Vinoth Kumar Deivasigamani
  • Patent number: 11556337
    Abstract: A matrix multiplication circuit comprises a memory storage device, processing circuitry, a parallel multiply circuit, and buffer circuits. The parallel multiply circuit simultaneously performs a count of multiplies in a parallel multiplication operation. The buffer circuits include prefetch buffer circuits each having a storage array dimension corresponding to the count of multiplies in the parallel multiplication operation. The processing circuitry loads a first prefetch buffer circuit with values from the first matrix; fetches a value of the second matrix and, in parallel with the fetch, preload the second prefetch buffer circuit with another value from the first matrix; initiates a parallel multiply of the fetched value of the second matrix and the values in the first prefetch buffer circuit; and stores partial product results of the parallel multiply, including adding a current partial product result to a previously stored partial product result.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: January 17, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: Praveen Chandrasekaran, Vinoth Kumar Rajasekar, Shreeja Sugathan
  • Patent number: 11550029
    Abstract: Delay calibration for digital signal chains of SFCW systems is disclosed. An example calibration method includes receiving a burst with a test pulse, the burst having a duration of L clock cycles; receiving a trigger indicative of a time when the burst was transmitted; generating a digital signal indicative of the received burst; for each of L clock cycles, computing a moving average of a subset of digital samples and an amplitude for each average; identifying one moving average for which the computed amplitude is closest to an expected amplitude; identifying the clock cycle of the identified moving average; and updating at least one delay to be applied in digital signal processing of received bursts based on a difference between the trigger and the identified clock cycle. The delay may be used for selecting digital samples of the received signal that contain valid data for performing further data processing.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: January 10, 2023
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Vinoth Kumar, Satishchandra G. Rao, Corey Petersen, Madhusudan Rathi, Gerard E. Taylor, Kaustubh Mundhada
  • Publication number: 20220364102
    Abstract: Disclosed herein are formulations and methods for the treatment of disease. The formulations and methods allow for the reprogramming of immune cells in a subject, particularly the T cells of a subject. The formulations are nanoparticles that have an interior and exterior in which the interior includes DNA molecules that encode genes for reprogramming T cells. The exterior of the nanoparticles targets the T cells to provide the DNA to the T cells.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 17, 2022
    Inventor: Vinoth Kumar Lakshmanan
  • Publication number: 20220337513
    Abstract: Embodiments herein facilitate the modification of data traffic load balancing on information handling systems affected by a networking information handling system having the status of one or more of its uplinks changed from operable to inoperable or from inoperable to operable. In one or more embodiments, an agent operating on or in conjunction with a networking information handling system (e.g., a TOR) detects a change in one its links. The agent sends a message to information handling system(s) (e.g., hosts) that are communicatively coupled to the TOR regarding the change in status. Based upon the TOR's message, a host may adjust its traffic load balancing to compensate for the status change. Embodiments, therefore, help efficiently utilize network pathways.
    Type: Application
    Filed: April 16, 2021
    Publication date: October 20, 2022
    Applicant: DELL PRODUCTS L.P.
    Inventors: Sudharsan Dhamal GOPALARATHNAM, Vinoth Kumar ARUMUGAM
  • Publication number: 20220329476
    Abstract: A method includes executing, on a processor of a computing device, instructions that cause the computing device to perform operations. The operations include executing, on a processor of a computing device, instructions that cause the computing device to perform operations. The operations include receiving site features associated with a communication site and receiving event features associated with a potential outage-causing event. A classifying engine is employed to generate an impact metric indicating an effect on the communication site from the potential outage-causing event based on the site features and the event features.
    Type: Application
    Filed: April 13, 2021
    Publication date: October 13, 2022
    Inventors: Allie Khalil Watfa, Nilam Jyoti Sharma, Manikandan Murugesan, Rajesh Pratabrai Lalwani, Adabel Jasmin Marquina, Vinoth Kumar Rajasekar
  • Publication number: 20220326945
    Abstract: A matrix multiplication circuit comprises a memory storage device, processing circuitry, a parallel multiply circuit, and buffer circuits. The parallel multiply circuit simultaneously performs a count of multiplies in a parallel multiplication operation. The buffer circuits include prefetch buffer circuits each having a storage array dimension corresponding to the count of multiplies in the parallel multiplication operation. The processing circuitry loads a first prefetch buffer circuit with values from the first matrix; fetches a value of the second matrix and, in parallel with the fetch, preload the second prefetch buffer circuit with another value from the first matrix; initiates a parallel multiply of the fetched value of the second matrix and the values in the first prefetch buffer circuit; and stores partial product results of the parallel multiply, including adding a current partial product result to a previously stored partial product result.
    Type: Application
    Filed: April 12, 2021
    Publication date: October 13, 2022
    Inventors: Praveen Chandrasekaran, Vinoth Kumar Rajasekar, Shreeja Sugathan