Abstract: This document describes systems and techniques for a hardware-based save-and-restore controller in an SoC. The described systems and techniques can automatically save and restore access control configurations (e.g., register states) of IP subsystems during a power-down and a power-up sequence, respectively. The save operation is initiated by a local save-and-restore (L SAR) controller and performed by the IP subsystems writing the configuration values to a central save-and-restore (C-SAR) controller before powering down a power domain. The C-SAR controller saves the configuration information in a memory located in an always-on power domain. The described systems and techniques initiate, via the L SAR controller, a restore operation as part of the power-up sequence. In this way, the described systems and techniques provide scalable save-and-restore services, support a large number of power domains, and allow a variable number of access control configurations to be saved and restored.

Abstract: If a secure element accesses a resource that is separate from the secure element, conducting a secure transaction can be inefficient in terms of power or time. Power usage is inefficient if the resource is never permitted to sleep, and transaction time is inefficient if the resource is permitted to sleep, and the user experiences a delay. To enable dual efficiency, a resource entity is permitted to be powered down. The resource entity is then powered up speculatively by an activation controller. The activation controller predicts an upcoming secure transaction based on sensor output, such as a position fix or a detected electromagnetic field. Based on monitored sensor output, the activation controller issues an activation signal to power up the secure element or the resource entity prior to initiation of the upcoming secure transaction. Thus, power can be conserved without introducing a transaction-processing latency.

Abstract: This document describes a secure element that leverages the resources of a computer system to perform specialized functions using sensitive information. The secure element securely stores sensitive information on flash memory of the computer system. In response to a request requiring use of sensitive information, the secure element loads a security application and sensitive information from the computer system. By leveraging external resources, the secure element may flexibly accommodate increasing resource requirements of the computer system and be used in a wide range of computer systems.

Abstract: Techniques for providing countermeasures against physical attacks on the contents of off-chip memory are provided in which a pseudo-internal memory resistant to physical attack is used. The pseudo-internal memory is mapped to an address space such that the pseudo-internal memory appears to be on-chip memory to a processor or a system on a chip (SoC). A method for protecting sensitive data according to these techniques includes presenting, by a pseudo-internal memory module of a SoC, an address space as internal memory of the SoC, where the address space comprises memory located off-chip from the system on a chip, receiving a data write request at the pseudo-internal memory module from a component of the SoC, encrypting data associated with the data write request using the pseudo-internal memory module to generate encrypted data, and writing the encrypted data to the memory located off-chip from the SoC.

Abstract: One feature pertains to an efficient procedure for storing data units in a storage device that allows for authentication of data units to prevent rollback attacks and other attacks such as cut-and-paste attacks. In one aspect, a message authentication code (MAC) is generated or otherwise obtained based on a primary key, a data unit to be stored, a corresponding index for the data unit (such as a page index) and a secondary key for the corresponding data unit, which is generated for each new write operation. The MAC and the corresponding data unit are stored in a bulk storage device such as a relatively insecure off-chip storage. Secondary keys are stored in a separate storage device such as a more secure on-chip storage. In some examples, new secondary keys are generated upon each data write based on a non-zero random or pseudorandom value.

Abstract: One feature pertains to encrypting data to improve data confidentiality. In one aspect, a modified form of XTS encryption is provided for use with reduced-round block ciphers. A data unit index of data to be applied to the reduced-round cipher is encrypted under a secret key to generate or otherwise obtain a modified secret key for applying to the reduced-round cipher. That is, data to be encrypted by the reduced-round cipher is not encrypted under a static key but is instead encrypted under a dynamic key that varies according to the index of the data. If an attacker were to derive the value of the key applied to the reduced-round cipher by analyzing data encrypted by the cipher, the attacker would only obtain the dynamic key corresponding to one particular data unit index, rather than a global static key applied to an entire address space. Decryption procedures are also described.

Abstract: One feature pertains to encrypting data to improve data confidentiality. In one aspect, a modified form of XTS encryption is provided for use with reduced-round block ciphers. A data unit index of data to be applied to the reduced-round cipher is encrypted under a secret key to generate or otherwise obtain a modified secret key for applying to the reduced-round cipher. That is, data to be encrypted by the reduced-round cipher is not encrypted under a static key but is instead encrypted under a dynamic key that varies according to the index of the data. If an attacker were to derive the value of the key applied to the reduced-round cipher by analyzing data encrypted by the cipher, the attacker would only obtain the dynamic key corresponding to one particular data unit index, rather than a global static key applied to an entire address space. Decryption procedures are also described.

Abstract: One feature pertains to an efficient procedure for storing data units in a storage device that allows for authentication of data units to prevent rollback attacks and other attacks such as cut-and-paste attacks. In one aspect, a message authentication code (MAC) is generated or otherwise obtained based on a primary key, a data unit to be stored, a corresponding index for the data unit (such as a page index) and a secondary key for the corresponding data unit, which is generated for each new write operation. The MAC and the corresponding data unit are stored in a bulk storage device such as a relatively insecure off-chip storage. Secondary keys are stored in a separate storage device such as a more secure on-chip storage. In some examples, new secondary keys are generated upon each data write based on a non-zero random or pseudorandom value.

Abstract: A bridge interfaces a first network protocol and a second network interface protocol. Each of a plurality of mapping windows is defined by corresponding mapping parameters defining a space in the first protocol and defining the mapping window translation rules to the second network protocol. Transaction requests in the first network protocol are selectively associated with the mapping windows.

Abstract: A device and method to perform memory operations at a clock domain crossing is disclosed. In a particular embodiment, a method includes providing a first clock signal to a write clock input of a memory to write data to the memory. The data is read from the memory according to a second clock signal that is different from the first clock signal. A third clock signal is provided to a read clock input of the memory. The third clock signal has a frequency that is substantially an integer multiple of a frequency of the second clock signal. The integer multiple is greater than one.

Abstract: A device and method to perform memory operations at a clock domain crossing is disclosed. In a particular embodiment, a method includes providing a first clock signal to a write clock input of a memory to write data to the memory. The data is read from the memory according to a second clock signal that is different from the first clock signal. A third clock signal is provided to a read clock input of the memory. The third clock signal has a frequency that is substantially an integer multiple of a frequency of the second clock signal. The integer multiple is greater than one.

Abstract: A bridge interfaces a first network protocol and a second network interface protocol. Each of a plurality of mapping windows is defined by corresponding mapping parameters defining a space in the first protocol and defining the mapping window translation rules to the second network protocol. Transaction requests in the first network protocol are selectively associated with the mapping windows.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.