Abstract: A shared memory video processor including signal processing circuitry. The signal processing circuitry may enable a noise reducer and a de-interlacer to share access to field buffers in a memory device to store various field lines. Some of the stored field lines may also be shared within the signal processing circuitry. The sharing of some stored field lines reduces overall memory bandwidth and capacity requirements. The signal processing circuitry may be capable of performing multiple field line processing. A set of field line buffers may be provided to store field lines for multiple field segments and may provide the data to the corresponding inputs of the signal processing circuitry. To further reduce storage, some of the field line buffers may also be shared among the signal processing circuitry.

Abstract: A scaler positioning module may receive a video signal selected from among a plurality of video signals. The scaler positioning module may include scaler slots for arranging the signal path of the selected video signal through at least one scaler in the scaler positioning module. The scaler slots may enable the scaler positioning module to operate in three modes. The three modes may enable the scaler positioning module to output scaled data without memory operations, scale prior to a memory write, and scale after a memory read. A blank time optimizer (BTO) may receive data from the scaler positioning module at a first clock rate and distributed memory accesses based on a bandwidth requirement determination. The BTO may access memory at a second clock rate. The second clock rate may be slower than the first which may reduce memory bandwidth and enable another video signal to access memory faster.

Abstract: Embodiments of the present disclosure provide a method that comprises, based at least on two frames of a plurality of frames of a video stream, performing interpolation according to an interpolation mode to generate one or more interpolation frames. The method also comprises determining a merit of the interpolation based on one or more of (i) a measure of errors of the interpolation, and (ii) a measure of accuracy of one or more occlusion or reveal regions of the one or more interpolation frames. The method further comprises dynamically changing the interpolation mode based at least on the determined merit of the interpolation.

Abstract: A system and method for modifying media stream based on a channel limitation are disclosed. In one embodiment, the system includes a channel analyzer, a modality of interest (MOI) identification module and an inter-modality resolution modification module. The channel analyzer determines a channel limitation. The MOI identification module receives a plurality of media streams and identifies at least one MOI. The inter-modality resolution modification module modifies a resolution of at least one of the media streams based on the channel limitation and content of the media streams. In another embodiment, the system includes a region of interest identification (ROI) module and an intra-modality resolution modification module instead of, or in addition to, the MOI identification module and inter-modality resolution modification module. The ROI identification module receives a media stream and identifies at least one ROI within the media stream.

Abstract: A system and method for modifying media stream based on a channel limitation are disclosed. In one embodiment, the system includes a channel analyzer, a modality of interest (MOI) identification module and an inter-modality resolution modification module. The channel analyzer determines a channel limitation. The MOI identification module receives a plurality of media streams and identifies at least one MOI. The inter-modality resolution modification module modifies a resolution of at least one of the media streams based on the channel limitation and content of the media streams. In another embodiment, the system includes a region of interest identification (ROI) module and an intra-modality resolution modification module instead of, or in addition to, the MOI identification module and inter-modality resolution modification module. The ROI identification module receives a media stream and identifies at least one ROI within the media stream.

Abstract: A system and method for scheduling a patient for remote, virtual consultation by a first available matching medical service provider are disclosed. In one embodiment, the system includes a classifier, a medical analyzer and a scheduler. The classifier associates a specialty with the first medical service provider (FMSP). The medical analyzer identifies a condition associated with the patient and identifies a specialty of medical service provider that can address the condition. The scheduler generates a list of patients waiting for medical consultation, receives an indication of availability of the FMSP, selects a patient from the list of patients based at least in part on whether the FMSP is associated with the specialty of medical service provider that can address the condition associated with the patient, checks for an available consultation device at a node associated with the patient, and assigns the FMSP for remote, virtual consultation with the patient.

Abstract: Devices, methods, and other embodiments associated with cadence detection are discussed. In one embodiment, an apparatus analyzes a progressive video stream and determines a cadence pattern from the progressive video stream.

Abstract: In one embodiment the present invention includes a digital image processing method for concealing errors. The method includes determining error pixel locations based on motion vectors and determining if the error pixel locations in a current frame are on an edge of an object in the current frame. If an error pixel location is on an edge, then a search of pixel values is performed in the current frame along the edge for a replacement pixel value. If the error pixel location is not on an edge, then a search of pixel values is performed in a region adjacent to the edge for the replacement pixel value.

Abstract: Systems and methods for converting a picture frame rate from a source video at a first rate to a target video at a second rate via interpolation of an intermediate frame. In one implementation, the system includes a phase plane correlation calculator including a low pass filter and a high pass filter for receiving previous frame data and current frame data where the phase plane correlation calculator is configured to generate a first motion vector based upon low pass representations and high pass representations. The system may also include a motion compensated interpolator that receives the first motion vector and an additional input motion vector and determines a final motion vector for use in interpolation. The system may further include an intermediate frame generator configured to generate the intermediate frame utilizing the final motion vector.

Abstract: Systems, methods, and other embodiments associated with image frame management are described. According to one embodiment, an apparatus includes classifier logic to categorize frames that represent an image as either reference frames or non-reference frames, where the categorization is based, at least in part, on motion vectors between the frames. The apparatus further includes management logic to store the reference frames and to delete the non-reference frames. Image generation logic may then reproduce the image by using the stored reference frames.

Abstract: A shared memory video processor including signal processing circuitry. The signal processing circuitry may enable a noise reducer and a de-interlacer to share access to field buffers in a memory device to store various field lines. Some of the stored field lines may also be shared within the signal processing circuitry. The sharing of some stored field lines reduces overall memory bandwidth and capacity requirements. The signal processing circuitry may be capable of performing multiple field line processing. A set of field line buffers may be provided to store field lines for multiple field segments and may provide the data to the corresponding inputs of the signal processing circuitry. To further reduce storage, some of the field line buffers may also be shared among the signal processing circuitry.

Abstract: A scaler positioning module may receive a video signal selected from among a plurality of video signals. The scaler positioning module may include scaler slots for arranging the signal path of the selected video signal through at least one scaler in the scaler positioning module. The scaler slots may enable the scaler positioning module to operate in three modes. The three modes may enable the scaler positioning module to output scaled data without memory operations, scale prior to a memory write, and scale after a memory read. A blank time optimizer (BTO) may receive data from the scaler positioning module at a first clock rate and distributed memory accesses based on a bandwidth requirement determination. The BTO may access memory at a second clock rate. The second clock rate may be slower than the first which may reduce memory bandwidth and enable another video signal to access memory faster.

Abstract: The invention includes a system and the associated method for decoding multiple video signals. The video signals may be component video, composite video or s-video signals each having multiple portions using a multimode video decoder. A selection stage may combine the multiple video signals and select some of their video signal portions for processing. The selection stage may time-multiplex some of the video signal portions. An analog to digital conversion stage may be shared by the time-multiplexing of the video signals. A decoder stage may decode the various signal portions and provide decoded output video signals. These feature may reduce the overall cost of the system. Various clock signals may be used to operate various stages of a multimode video decoder. Some of the clock signals may run at different frequencies and others may operate at a different phase.

Abstract: A motion compensated picture rate converter for determining a dominant motion vector for a block appearing in two images includes a high-pass filter and a low-pass filter, transform calculators responsive to the filters for performing transforms on at least two images to produce a frequency-domain representation of the images, estimating calculators for estimating a plurality of motion vectors based on the frequency-domain representations, and a periodic structure detection and elimination module responsive to the transform calculators and the estimating calculators for identifying a period based on the frequency-domain representation of the images and for selecting a dominant motion vector based on the estimated motion vectors and the identified period. A method of operation is also disclosed.

Abstract: A method for detecting edges includes calculating a gradient level value for each pixel of a digital image and assigning each pixel to one of a plurality of gradient bins based on the calculated gradient level value for each pixel, the gradient bins being defined by threshold levels. One or more of the gradient bins are assigned as edge bins, and one or more of the gradient bins are assigned as non-edge bins according to the number of pixels assigned to each gradient bin. Pixels in the one or more edge bins are identified as edge pixels, and pixels in the one or more non-edge bins are identified as non-edge pixels in an edge map. The one or more gradient bins are assigned such that a minimum number of pixels are identified as edge pixels and no more than a maximum number of pixels are identified as edge pixels.

Abstract: A shared memory video processor including signal processing circuitry. The signal processing circuitry may enable a noise reducer and a de-interlacer to share access to field buffers in a memory device to store various field lines. Some of the stored field lines may also be shared within the signal processing circuitry. The sharing of some stored field lines reduces overall memory bandwidth and capacity requirements. The signal processing circuitry may be capable of performing multiple field line processing. A set of field line buffers may be provided to store field lines for multiple field segments and may provide the data to the corresponding inputs of the signal processing circuitry. To further reduce storage, some of the field line buffers may also be shared among the signal processing circuitry.

Abstract: The invention includes a system and the associated method for decoding multiple video signals. The video signals may be component video, composite video or s-video signals each having multiple portions using a multimode video decoder. A selection stage may combine the multiple video signals and select some of their video signal portions for processing. The selection stage may time-multiplex some of the video signal portions. An analog to digital conversion stage may be shared by the time-multiplexing of the video signals. A decoder stage may decode the various signal portions and provide decoded output video signals. These feature may reduce the overall cost of the system. Various clock signals may be used to operate various stages of a multimode video decoder. Some of the clock signals may run at different frequencies and others may operate at a different phase.

Abstract: Systems and methods for identifying motion between a previous frame and a current frame. The system may include a fast Fourier transform calculator that generates low pass frequency domain outputs and high pass frequency domain outputs of previous frame data and current frame data. The system may further include a phase difference calculator that calculates a first phase difference between the low pass frequency domain outputs and a second phase difference between the high pass frequency domain outputs. An inverse Fourier transform calculator may be included to generate a first inverse Fourier result and a second inverse Fourier result based on the first and second phase difference respectively, and a motion vector calculator may be included for generating motion vectors based on the inverse Fourier results.

Abstract: A scaler positioning module may receive a video signal selected from among a plurality of video signals. The scaler positioning module may include scaler slots for arranging the signal path of the selected video signal through at least one scaler in the scaler positioning module. The scaler slots may enable the scaler positioning module to operate in three modes. The three modes may enable the scaler positioning module to output scaled data without memory operations, scale prior to a memory write, and scale after a memory read. A blank time optimizer (BTO) may receive data from the scaler positioning module at a first clock rate and distributed memory accesses based on a bandwidth requirement determination. The BTO may access memory at a second clock rate. The second clock rate may be slower than the first which may reduce memory bandwidth and enable another video signal to access memory faster.

Abstract: Systems and methods for converting a picture frame rate between a source video at a first rate and a target video at a second rate. A system may include a phase plane correlation calculator configured to determine a first motion vector estimate. The system may further include a global motion calculator configured to determine a second motion vector estimate based on the previous frame data, the current frame data, and the first motion vector estimate. The system may also include a motion compensated interpolator for assigning a final motion vector through a quality calculation and an intermediate frame generator for generating the intermediate frame using the final motion vector.