Abstract: An autonomous moving highway system including an elevated guideway having a support pier with a pier cap having a first end, a second end, an upper portion and a lower portion, where the lower portion of the pier cap is attached to the top end of the support pier, a first girder located at the first end of the pier cap and a second girder located at the second end of the pier cap, a first magnetically levitated (maglev) transportation track mounted to a bottom of the first girder and a second maglev transportation track mounted to a bottom of the second girder, a plurality of individual transportation pods, each transportation pod is configured to enclose a vehicle and at least one passenger of the vehicle, a computer control system configured to control power, propulsion, direction and motion of the plurality of transportation pods.

Abstract: A dynamic random access memory (DRAM) (10) is disclosed. Memory cell arrays (12) within the DRAM have word lines and bit lines, the bit lines being logically divided into bit line sections (26a-p). Corresponding to each bit line section (26a-p) is a sense/decode section (28a-p) having a fast and slow sense mode of operation. When data are read from a particular bit line section (26a-p) the corresponding sense decode section (28a-p) operates in the fast sense mode while the remaining sense/decode sections (28a-p) operate in the slow sense mode, providing for lower power consumption and/or faster access speeds.

Abstract: A word line driver circuit (10) for driving four word lines (18) is disclosed. In a preferred embodiment, the word line driver circuit (10) includes a decoder circuit (12) for pulling a decode node (20) to a logic low level (Vss) in response to internal row decode signals, a pull-up circuit (14) for pulling the decode node (20) to a logic high (Vcc) to deselect the word lines (18), four transfer transistors (NO) intermediate the decode node (20) and four control nodes (22), four CMOS inverters (18), each driving one word line (18) between a boost voltage and Vss. A PMOS level shifter transistor (P0) is associated with each inverter (18), and has a channel width that is small relative to both the channel widths of the transfer transistors (N0) and to the devices making up the decoder circuit (12), allowing the level shifter transistors (P0) to be overpowered by the decoder circuit (12).

Abstract: A burst dynamic random access memory (DRAM) (10) is disclosed having memory cells arranged in a number of quadrants (22), each quadrant including local I/O lines (24) for accessing the memory cells therein. The local I/O lines (24) of each quadrant are commonly coupled to global I/O lines (26) by tri-state driver banks (30). According to a row address and a first portion of a column address, a row decoding circuit (36) and column decoding circuit (40) couple one set of local I/O lines (24) within each quadrant (22) to selected columns within the quadrants (22). A bank sequencer (48) receives a second portion of the column address and generates burst sequence of different bank select signals. Each bank select signal enables a different set of tri-state driver banks (30). The enabled tri-state driver banks (30) provide a data path between the local I/O lines (24) and the global I/O lines.

Abstract: A synchronous memory device is provided in which a timing and control circuit (28) receives timing and control inputs. A row address buffer (38) and row decoders (40 and 42) operate to enable rows in plural memory sections (30, 32, 34, and 36). Column decoders (58, 60, 62, and 64) operate to enable columns in each of the memory sections (respectively, 32, 36, 30 and 34). The column decoders (58, 60, 62, and 64) decode addresses received from counters (respectively 52, 54, 48, and 50), an adder (46), and a latch (56). Counters (48, 50, 52, and 54) and adder (46) generate column addresses for each memory section based on a starting address, thereby allowing for internal operation at less than the external system frequency. Furthermore, an input buffer (100) is provided that allows data input to the memory device to be received at the system frequency. Once data for each memory section has been received, a substantially simultaneous write operation is performed to each unmasked memory section.

Abstract: A method and apparatus for testing the self-refresh operation of a dynamic memory part are provided in which an oscillator (140) is coupled to a self-refresh counter (142). The self-refresh counter (142) causes a refresh row address counter (144) to generate row addresses for self-refresh cycles. The refresh row address counter (144) is coupled to a self-refresh control circuit (148). The self-refresh control circuit (148) is operable to generate a signal indicating completion of a self-refresh cycle. The refresh row address counter (144) is also coupled to a multiplexer (146). The multiplexer (146) outputs row addresses from either the refresh row address counter (144) or those supplied externally for rows to be refreshed.

Abstract: A DRAM furnishes power management circuits that remove power from circuits on the DRAM that are not necessary for self-refresh and that turn on and off other circuits necessary for self-refresh in timed relation to the refresh cycle. The power management circuits include a counter and simple decoder circuits that decode the binary output of the counter.