Patents by Inventor Viren Agarwal

Viren Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System, method, and computer program product for electronic design visualization
    Patent number: 9645715
    Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include receiving, using at least one processor, an electronic design and displaying, at a graphical user interface, at least a portion of the electronic design. Embodiments may also include allowing a user to select at least one design variable at the graphical user interface. Embodiments may also include simulating the electronic design, based upon, at least in part, the selected at least one design variable and in response to the simulation, automatically displaying an updated value at the graphical user interface.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: May 9, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Abha Jain, Hitesh Mohan Kumar, Parag Choudhary, Viren Agarwal
  • Efficient method for mapping a logic design on field programmable gate arrays
    Patent number: 7676782
    Abstract: An efficient method for mapping a logic design on Field Programmable Gate Arrays involves a determination of the minimum required square grid of FPGA logic blocks for mapping the design, providing a compensation factor on the minimum square grids, selecting the maximum value among the compensated square grids for reducing the mapping time; and implementing a legalization adjustment to ensure mapping of said compensated design.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: March 9, 2010
    Inventors: Dhabalendu Samanta, Viren Agarwal
  • Efficient method for mapping a logic design on field programmable gate arrays
    Publication number: 20060190906
    Abstract: An efficient method for mapping a logic design on Field Programmable Gate Arrays involves a determination of the minimum required square grid of FPGA logic blocks for mapping the design, providing a compensation factor on the minimum square grids, selecting the maximum value among the compensated square grids for reducing the mapping time; and implementing a legalization adjustment to ensure mapping of said compensated design.
    Type: Application
    Filed: December 27, 2005
    Publication date: August 24, 2006
    Inventors: Dhabalendu Samanta, Viren Agarwal