Patents by Inventor Virendra R. Jadhav

Virendra R. Jadhav has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090146316
    Abstract: Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap) of each metal layer provides a landing spot for a solder joint between an integrated circuit device and the substrate and, thereby, allows for enhanced solder volume control. The additional structural support, in combination with the enhanced solder volume control, minimizes strain on the resulting solder joints. Additionally, the cap further allows the minimum diameter of the solder joint on the substrate-side of the assembly to be larger than the diameter of the solder resist opening. Thus, the invention decouples C4 reliability concerns from laminate design concerns and, thereby, allows for greater design flexibility.
    Type: Application
    Filed: December 5, 2007
    Publication date: June 11, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Jayshree Shah, Kamalesh K. Srivastava
  • Publication number: 20090095502
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: October 11, 2007
    Publication date: April 16, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: VIRENDRA R. JADHAV, KRYSTYNA W. SEMKOW, KAMALESH K. SRIVASTAVA, BRIAN R. SUNDLOF
  • Publication number: 20080313879
    Abstract: A tensile strength testing structure for controlled collapse chip connections (C4) disposed above a substrate includes: a fixture base configured for positioning substrates with C4; a top fixture plate with through hole channels; test pins for insertion through the through hole channels; wherein dimensional tolerances of the substrates are accounted for with openings on at least two sides of the fixture base for positioning the substrates, and during alignment of the top fixture plate through hole channels with the C4 prior to securing the top fixture plate to the fixture base; wherein the test pins are strain hardened metal wires; wherein lower ends of the test pins are joined to the C4 during a solder reflow process; and wherein distal ends of the test pins are pulled in a direction perpendicular to the testing structure to determine the tensile strength of the C4.
    Type: Application
    Filed: June 22, 2007
    Publication date: December 25, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Vijayeshwar D. Khanna, David C. Long, David L. Questad
  • Publication number: 20080142968
    Abstract: A structure for controlled collapse chip connection disposed above a substrate. The substrate has two faces, with the second face being disposed substantially parallel to the first face. A contact pad in signal communication with the integrated circuit is disposed on the second face. A first passivation layer forms a first angled aperture substantially above the contact pad. The angled aperture increasing in circumference with increasing distance from the contact pad. A ball-limiting metallurgy (BLM) disposed within the aperture, with a center section in signal communication with the contact pad, an angled section extending away from the center portion and terminated in an edge section. A second passivation layer disposed on the first passivation layer, and partially encapsulating the edge region of the BLM with a second angled aperture. The shape and slope of the BLM and the second angled aperture controls the formation of a solder ball.
    Type: Application
    Filed: December 15, 2006
    Publication date: June 19, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Scott P. Moore
  • Patent number: 7088008
    Abstract: An electronic package, such as a chip carrier, with an optimized circuit pattern having a circuitized substrate with a first and second circuit pattern is provided. The circuitized substrate includes a corner surface region. The second circuit pattern is electrically connected to the first circuit pattern on the corner surface region of the circuitized substrate and is positioned in such a manner so as to substantially inhibit cracking of the first circuit pattern during flexure of the chip carrier.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: David J. Alcoe, William Infantolino, Virendra R. Jadhav
  • Publication number: 20040183211
    Abstract: An electronic package, such as a chip carrier, with an optimized circuit pattern having a circuitized substrate with a first and second circuit pattern is provided. The circuitized substrate includes a corner surface region. The second circuit pattern is electrically connected to the first circuit pattern on the corner surface region of the circuitized substrate and is positioned in such a manner so as to substantially inhibit cracking of the first circuit pattern during flexure of the chip carrier.
    Type: Application
    Filed: March 20, 2003
    Publication date: September 23, 2004
    Applicant: International Business Machines Corporation
    Inventors: David J. Alcoe, William Infantolino, Virendra R. Jadhav
  • Patent number: 6703704
    Abstract: An electronic structure and associated method of formation. A laminate is solderably coupled to an electronic carrier. A stiffener is adhesively attached to a portion of a surface of the laminate by a stiffener adhesive that is in physically adhesive contact with a portion of a first surface of the stiffener and with the portion of the surface of the laminate. A thermal lid is adhesively attached to a portion of a second surface of the stiffener by a lid adhesive that is in physically adhesive contact with a portion of a surface of the lid and with a portion of the second surface of the stiffener. A void region is disposed between the surface of the thermal lid and the surface of the laminate.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: March 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: David J. Alcoe, Kim J. Blackwell, Virendra R. Jadhav