Patents by Inventor Viresh Piyush Patel

Viresh Piyush Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11894352
    Abstract: A power electronic module is provided that includes an electrical connection on opposing surfaces of an electronic component that allows a high current path from a top board to a bottom board through the body of the electronic component thus improving the power electronic module's electrical resistance and reducing the current load on the connector structure which is located between the first substrate and the second substrate. The power electronic module further includes a semiconductor component positioned on an external surface of the top board which allows for thermal contact of the semiconductor component with an external heat sink thus providing an efficient system thermal management via a reduced heat dissipation path. Additional heat dissipation can be obtained by disposing a metallic spacer on the semiconductor component of the power electronic module of the present disclosure.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: February 6, 2024
    Assignee: Renesas Electronics America Inc.
    Inventors: Sri Ganesh A Tharumalingam, Mark Kwoka, Viresh Piyush Patel, Peter Zhizheng Liu, Jeff Strang
  • Publication number: 20220375909
    Abstract: A power electronic module is provided that includes an electrical connection on opposing surfaces of an electronic component that allows a high current path from a top board to a bottom board through the body of the electronic component thus improving the power electronic module's electrical resistance and reducing the current load on the connector structure which is located between the first substrate and the second substrate. The power electronic module further includes a semiconductor component positioned on an external surface of the top board which allows for thermal contact of the semiconductor component with an external heat sink thus providing an efficient system thermal management via a reduced heat dissipation path. Additional heat dissipation can be obtained by disposing a metallic spacer on the semiconductor component of the power electronic module of the present disclosure.
    Type: Application
    Filed: May 18, 2021
    Publication date: November 24, 2022
    Applicant: Renesas Electronics America Inc.
    Inventors: Sri Ganesh A Tharumalingam, Mark Kwoka, Viresh Piyush Patel, Peter Zhizheng Liu, Jeff Strang
  • Patent number: 9478599
    Abstract: An integrated circuit device includes an integrated circuit substrate having an at least two piece package thereon. The package has a sealed cavity therein and a patterned metal inductor in the cavity. The inductor has at least a first terminal electrically coupled to a portion of the integrated circuit substrate by an electrically conductive via, which extends at least partially through the package. The package, which may include a material selected from a group consisting of glass and ceramics, includes a base and a cap sealed to the base. The metal inductor includes a metal layer patterned on at least one of the cap and base of the package. The base may also include first and second electrically conductive vias therein, which are electrically connected to first and second terminals of the inductor.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: October 25, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Robert A. Gubser, Ajay Kumar Ghai, Viresh Piyush Patel
  • Patent number: 9445536
    Abstract: A crystal oscillator fabrication method includes depositing mounting cement onto first and second mounting pads on a substrate to thereby define first and second electrode adhesion bumps. First and second electrodes of a crystal oscillator are electrically connected to the first and second mounting pads by contacting the first and second electrodes to the first and second electrode adhesion bumps and then curing the adhesion bumps. Next, mounting cement is deposited onto the first electrode and onto a portion of the first electrode adhesion bump to thereby define a top electrode adhesion extension. The top electrode adhesion extension is then cured.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 13, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Robert A. Gubser, Ajay Kumar Ghai, Viresh Piyush Patel
  • Patent number: 9397151
    Abstract: A packaged integrated circuit includes an integrated circuit substrate and a cap bonded to a surface of the integrated circuit substrate. The cap has a recess therein that is at least partially lined with at least one segment of an inductor. This inductor may be electrically coupled to an electrical component within the integrated circuit substrate. In some embodiments, the inductor is patterned to extend along a sidewall and interior top surface of the recess, which extends opposite the integrated circuit substrate. The inductor may include a plurality of arcuate-shaped segments and may be patterned to be symmetric about a center-tapped portion thereof. The cap may also include a magnetic material therein that increases an effective inductance of the inductor relative to an otherwise equivalent cap and inductor combination that is devoid of the magnetic material.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 19, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Kenneth L. Astrof, Robert A. Gubser, Ajay Kumar Ghai, Viresh Piyush Patel, Jitesh Shah
  • Patent number: 9306537
    Abstract: An integrated circuit device includes an integrated circuit substrate having a two piece package thereon. The package has a hermetically sealed cavity therein and a crystal resonator within the cavity. The crystal resonator includes at least one electrode electrically coupled to a portion of the integrated circuit substrate by an electrically conductive via, which extends at least partially through the package. The package may include a material selected from a group consisting of glass and ceramics. The crystal resonator includes a crystal blank and first and second electrodes on first and second opposing sides of the crystal blank. The package includes a base having a recess therein and a cap hermetically sealed to the base. The cap includes first and second electrical traces thereon, which are electrically connected to the first and second electrodes of the crystal resonator.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: April 5, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Robert A. Gubser, Ajay Kumar Ghai, Viresh Piyush Patel