Abstract: A light source driver circuit is provided that has at least first and second current source circuits that are electrically coupled to a node of the driver circuit. The first and second current source circuits source first and second fractions, respectively, of a total current needed to drive a light source into a node of the driver circuit. The driver circuit uses a sum of the first and second fractions of the total current in combination with a modulation current to drive the light source. By incorporating at least first and second current source circuits into the driver circuit, each of the current sources can be kept sufficiently small in size that they contribute very little parasitic capacitance, and therefore allow the driver circuit to achieve high-bandwidth operations while also allowing the driver circuit to operate at a low supply voltage.

Abstract: A light source driver circuit is provided that has at least first and second current source circuits that are electrically coupled to a node of the driver circuit. The first and second current source circuits source first and second fractions, respectively, of a total current needed to drive a light source into a node of the driver circuit. The driver circuit uses a sum of the first and second fractions of the total current in combination with a modulation current to drive the light source. By incorporating at least first and second current source circuits into the driver circuit, each of the current sources can be kept sufficiently small in size that they contribute very little parasitic capacitance, and therefore allow the driver circuit to achieve high-bandwidth operations while also allowing the driver circuit to operate at a low supply voltage.

Abstract: A variable gain amplifier circuit includes a differential pair of transistors and a variable current source circuit. The differential pair of transistors generates an output signal based on an input signal. The variable current source circuit is coupled to the differential pair of transistors. A gain of the output signal relative to the input signal varies in response to variations in a bias current through the variable current source circuit. The variable gain amplifier circuit maintains a common mode voltage of the output signal substantially constant in response to the variations in the bias current through the variable current source circuit.

Abstract: An integrated circuit may include receiver circuitry that receives data from an external device. Such receiver circuitry may include, among other things, equalization circuitry that may reconstruct the received data before transmitting the received data to other parts of the integrated circuit. The receiver circuitry may include two different equalization circuits. A first equalization circuit may perform equalization on the received data to generate a first equalized output while a second equalization circuit may generate a second equalized output. The receiver circuitry may further include an amplifier circuit that selectively amplifies either the first or second equalized output from the respective first and second equalization circuits based on the data rate of the received data.

Abstract: Disclosed is a circuit architecture for cancellation of threshold voltage offsets for an array of sense amplifiers. An offset calibration controller, which may be embedded as a hard-wired circuit in the transceiver core circuits, writes the offset adjustment values to a memory-mapped interface circuit. The memory-mapped interface circuit outputs the offset adjustment values to offset adjustment circuits for the sense amplifiers. The offset adjustment circuits may utilize a body bias technique. Advantageously, the disclosed circuit architecture provides for the minimization of residual offset without sacrificing bandwidth. Other embodiments, features and advantages are also disclosed.

Abstract: In one embodiment, an integrated circuit current mirror circuit is disclosed. The integrated circuit current mirror circuit includes a reference circuit, an output circuit and a mode selector circuit. The reference circuit includes an input terminal that receives a reference current. The output circuit generates an output current that is proportional to the reference current. The output circuit is coupled to a load circuit. The output current is provided to the load circuit. The mode selector circuit is coupled to the reference circuit and the output circuit. The mode selector circuit receives a plurality of mode control signals having different voltage levels. The mode selector circuit selects one of the mode control signals. The selected mode control signal is routed to the reference circuit and the output circuit to place the current mirror circuit in a desired mode.

Abstract: An integrated circuit having transceiver circuitry is provided. The transceiver circuitry may include an equalization circuit such as a decision feedback equalizer (DFE). The DFE may include a variable gain amplifier (VGA) that is coupled to a summation node circuit and a digital sampler. The DFE may also include an operational amplifier that is coupled in a negative feedback loop and that provides a controlled power supply voltage to the VGA so that the VGA is able to provide a stable common mode output voltage to the digital sampler. The operational amplifier may be a self-biased operational amplifier with an output stage that includes miller compensation circuitry for enhanced stability.