Abstract: A method for forming a semiconductor device is provided. The method includes forming a semiconductor layer. The method further includes forming a gate structure overlying the semiconductor layer. The method further includes forming a high-k sidewall spacer adjacent to the gate structure. The method further includes forming a recess in the semiconductor layer, the recess aligned to the high-k sidewall spacer. The method further includes forming an in-situ doped epitaxial material in the recess, the epitaxial material having a natural lattice constant different from a lattice constant of the semiconductor layer to create stress in a channel region of the semiconductor device.

Abstract: An improved varactor diode (40) is obtained by providing a substrate (41) having a first surface (43), in which are formed a P+ region (53, 46) proximate the first surface (43), a first N region (54, 45) located beneath the P+ region (53, 46), an N well region (56, 44) located beneath the first N region (54, 45) and a first P counter-doped region (55) located between the first N region (54, 45) and the N well region (56, 44), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region (59) is provided within the N-well region (56, 44) so as to reduce the N doping concentration within the N well region (56, 44) but without creating a further PN junction therein. The net doping profile (52) provides varactor diodes (40) having a larger tuning ratio than varactors (20) without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.

Abstract: A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure overlies the dielectric layer and has a first current electrode and a second current electrode separated by a channel. A floating gate has a vertical portion that is adjacent to and electrically insulated from a side of the channel and has a horizontal portion overlying the first dielectric layer and extending laterally away from the channel. The floating gate stores electrical charge. A second dielectric layer is adjacent the floating gate. A control gate adjacent the second dielectric layer and physically separated from the floating gate by the second dielectric layer. The “L-shape” of the floating gate enhances capacitive coupling ratio between the control gate and the floating gate.

Abstract: High frequency performance of (e.g., silicon) bipolar devices (100, 100?) is improved by reducing the extrinsic base resistance Rbx. Emitter (160), base (161) and collector (190) are formed in or on a semiconductor substrate (110). The emitter contact (154) has a portion (154?) that overhangs a portion (1293, 293?) of the extrinsic base contact (129), thereby forming a cave-like cavity (181, 181?) between the overhanging portion (154?) of the emitter contact (154) and the underlying regions (1293, 1293?) of the extrinsic base contact (129). When the emitter contact and the extrinsic base contact are silicided, some of the metal atoms forming the silicide penetrate into the cavity (181, 181?) so that the highly conductive silicided extrinsic base contact extends under the edge of the emitter contact (154?) closer to the base (161, 163) itself, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.

Abstract: A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.

Abstract: A process of forming an electronic device can include forming a gate electrode layer and forming a patterned masking layer. In a first aspect, a process operation is performed before removing substantially all of a lower portion of the gate electrode layer. In a second aspect, a gate dielectric layer is formed prior to forming the gate electrode layer, and a portion of the gate dielectric layer is exposed after removing the patterned masking layer and prior to forming another masking layer. A portion of the gate electrode layer remains covered during a process where some or all of the portion would be otherwise removed or consumed. By forming the electronic device using such a process, damage to the gate electrode structure while performing subsequent processing can be significantly reduced.

Abstract: A semiconductor device is formed using a semiconductor substrate. A gate dielectric is formed over the semiconductor substrate. A gate electrode layer is formed over the gate dielectric. A patterned masking layer is formed over the gate electrode layer. A first region of the gate electrode layer lies within an opening in the patterned masking layer. The first region of the gate electrode layer is partially etched to leave an elevated portion of the gate electrode layer and a lower portion adjacent to the elevated portion. A sidewall spacer is formed adjacent to the elevated portion and over the lower portion. An implant is performed into the semiconductor substrate using the elevated portion and the sidewall spacer as a mask. The sidewall spacer and the lower portion are removed.

Abstract: A method for making a semiconductor structure (10) includes providing a wafer with a structure (16) having a sidewall, forming a sidewall spacer (22) adjacent to the sidewall, and forming a layer of material (28) over the wafer including over the sidewall spacer and over the structure having the sidewall. The method further includes etching the layer, wherein the etching (i) leaves at least portions of the sidewall spacer exposed and (ii) leaves a portion of the layer located over the structure having a sidewall. The portion of the layer located over the structure having a sidewall is reduced in thickness by the etching. Subsequent to etching the layer, the method includes removing the sidewall spacer.

Abstract: An improved varactor diode (40) is obtained by providing a substrate (41) having a first surface (43), in which are formed a P+ region (53, 46) proximate the first surface (43), a first N region (54, 45) located beneath the P+ region (53, 46), an N well region (56, 44) located beneath the first N region (54, 45) and a first P counter-doped region (55) located between the first N region (54, 45) and the N well region (56, 44), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region (59) is provided within the N-well region (56, 44) so as to reduce the N doping concentration within the N well region (56, 44) but without creating a further PN junction therein. The net doping profile (52) provides varactor diodes (40) having a larger tuning ratio than varactors (20) without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.

Abstract: An improved varactor diode (40) is obtained by providing a substrate (70) having a first surface (73) and in which are formed a first N region (46) having a first peak dopant concentration (47) located at a first depth (48) beneath the surface (73), and a first P region having a second peak dopant concentration (50) greater than the first peak dopant concentration located at a second depth (51) beneath the surface less than the first depth (48), and a second P region (42) having a third peak dopant concentration (43) greater than the second peak dopant concentration and located at a third depth at or beneath the surface (73) less than the second depth (51), so that the first P region (49) provides a retrograde doping profile whose impurity concentration increases with distance from the inward edge (44) of the second P region (42) up to the second peak dopant concentration (50).

Abstract: High frequency performance of (e.g., silicon) bipolar devices (100, 100?) is improved by reducing the extrinsic base resistance Rbx. Emitter (160), base (161) and collector (190) are formed in or on a semiconductor substrate (110). The emitter contact (154) has a portion (154?) that overhangs a portion (1293, 293?) of the extrinsic base contact (129), thereby forming a cave-like cavity (181, 181?) between the overhanging portion (154?) of the emitter contact (154) and the underlying regions (1293, 1293?) of the extrinsic base contact (129). When the emitter contact and the extrinsic base contact are silicided, some of the metal atoms forming the silicide penetrate into the cavity (181, 181?) so that the highly conductive silicided extrinsic base contact extends under the edge of the emitter contact (154?) closer to the base (161, 163) itself, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.

Abstract: A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure overlies the dielectric layer and has a first current electrode and a second current electrode separated by a channel. A floating gate has a vertical portion that is adjacent to and electrically insulated from a side of the channel and has a horizontal portion overlying the first dielectric layer and extending laterally away from the channel. The floating gate stores electrical charge. A second dielectric layer is adjacent the floating gate. A control gate adjacent the second dielectric layer and physically separated from the floating gate by the second dielectric layer. The “L-shape” of the floating gate enhances capacitive coupling ratio between the control gate and the floating gate.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a semiconductor layer. The method further includes forming a gate structure overlying the semiconductor layer. The method further includes forming a high-k sidewall spacer adjacent to the gate structure. The method further includes forming a recess in the semiconductor layer, the recess aligned to the high-k sidewall spacer. The method further includes forming an in-situ doped epitaxial material in the recess, the epitaxial material having a natural lattice constant different from a lattice constant of the semiconductor layer to create stress in a channel region of the semiconductor device.

Abstract: A strained semiconductor layer is achieved by a method for transferring stress from a dielectric layer to a semiconductor layer. The method comprises providing a substrate having a semiconductor layer. A dielectric layer having a stress is formed over the semiconductor layer. A radiation anneal is applied over the dielectric layer of a duration not exceeding 10 milliseconds to cause the stress of the dielectric layer to create a stress in the semiconductor layer. The dielectric layer may then be removed. At least a portion of the stress in the semiconductor layer remains in the semiconductor layer after the dielectric layer is removed. The radiation anneal can be either by using either a laser beam or a flash tool. The radiation anneal can also be used to activate source/drain regions.

Abstract: A method of forming a doped region includes, in one embodiment, implanting a dopant into a region in a semiconductor substrate, recrystallizing the region by performing a first millisecond anneal, wherein the first millisecond anneal has a first temperature and a first dwell time, and activating the region using as second millisecond anneal after recrystallizing the region, wherein the second millisecond anneal has a second temperature and a second dwell time. In one embodiment, the first millisecond anneal and the second millisecond anneal use a laser. In one embodiment, the first temperature is the same as the second temperature and the first dwell time is the same as the second dwell time. In another embodiment, the first temperature is different from the second temperature and the first dwell time is different from the second dwell time.

Abstract: A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).

Abstract: A method for making a semiconductor structure (10) includes providing a wafer with a structure (16) having a sidewall, forming a sidewall spacer (22) adjacent to the sidewall, and forming a layer of material (28) over the wafer including over the sidewall spacer and over the structure having the sidewall. The method further includes etching the layer, wherein the etching (i) leaves at least portions of the sidewall spacer exposed and (ii) leaves a portion of the layer located over the structure having a sidewall. The portion of the layer located over the structure having a sidewall is reduced in thickness by the etching. Subsequent to etching the layer, the method includes removing the sidewall spacer.

Abstract: A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.

Abstract: A semiconductor device is formed using a semiconductor substrate. A gate dielectric is formed over the semiconductor substrate. A gate electrode layer is formed over the gate dielectric. A patterned masking layer is formed over the gate electrode layer. A first region of the gate electrode layer lies within an opening in the patterned masking layer. The first region of the gate electrode layer is partially etched to leave an elevated portion of the gate electrode layer and a lower portion adjacent to the elevated portion. A sidewall spacer is formed adjacent to the elevated portion and over the lower portion. An implant is performed into the semiconductor substrate using the elevated portion and the sidewall spacer as a mask. The sidewall spacer and the lower portion are removed.

Abstract: A process of forming an electronic device can include forming a gate electrode layer and forming a patterned masking layer. In a first aspect, a process operation is performed before removing substantially all of a lower portion of the gate electrode layer. In a second aspect, a gate dielectric layer is formed prior to forming the gate electrode layer, and a portion of the gate dielectric layer is exposed after removing the patterned masking layer and prior to forming another masking layer. A portion of the gate electrode layer remains covered during a process where some or all of the portion would be otherwise removed or consumed. By forming the electronic device using such a process, damage to the gate electrode structure while performing subsequent processing can be significantly reduced.