Abstract: Field effect transistors having field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, and methods of fabricating field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, are described. In an example, an integrated circuit structure includes a semiconductor channel structure including a monocrystalline material. A gate dielectric is over the semiconductor channel structure, the gate dielectric including a high-k dielectric layer on a dipole material layer, and the dipole material layer distinct from the high-k dielectric layer. A gate electrode has a workfunction layer on the high-k dielectric layer, the workfunction layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.

Abstract: An apparatus for a communication device, the apparatus may include a processor configured to: obtain channel metrics for a plurality of radio communication channels, each obtained channel metric is associated with a respective radio communication channel of the plurality of radio communication channels, generate a plurality of channel hopping sequences, each channel hopping sequence is representative of an allocation of the plurality of radio communication channels for a plurality of time slots, wherein a number of time slots allocated for each radio communication channel within each channel hopping sequence is based on the respective obtained channel metric, and select one of the plurality of channel hopping sequences based on a predefined criterion to communicate with a further communication device.

Abstract: Mushroomed via structures for trench contact or gate contact are described. In an example, an integrated circuit structure includes a trench contact structure over an epitaxial source or drain structure. A dielectric layer is over the trench contact structure. A trench contact via is in an opening in the dielectric layer, the trench contact via in contact with the trench contact structure. A trench contact via extension is on the trench contact via. The trench contact via extension above the dielectric layer and extending laterally beyond the trench contact via.

Abstract: An integrated circuit (IC), including a functional circuit and a security system, is disclosed. The functional circuit generates a request packet for an indirect memory access of a memory. The security system validates the functional circuit based on a security attribute and a functional identifier of the functional circuit. Based on the request packet and the validation of the functional circuit, the security system identifies an instruction sequence associated with the indirect memory access. Further, the security system determines a type of the indirect memory access based on the instruction sequence, and validates the type of the indirect memory access based on the security attribute and the request packet. Based on the validation of the type of the indirect memory access, the instruction sequence is executed, thereby facilitating the indirect memory access for the functional circuit.

Abstract: Embodiments disclosed herein include integrated circuit structures and methods of forming such structures. In an embodiment, an integrated circuit structure comprises a dielectric layer with a first surface and a second surface, and an opening through the dielectric layer. In an embodiment, the opening is defined by sidewalls. In an embodiment, a graphene liner contacts the first surface of the dielectric layer and the sidewalls of the opening. In an embodiment, a conductive material at least partially fills a remainder of the opening.

Abstract: Field effect transistors having field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, and methods of fabricating field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, are described. In an example, an integrated circuit structure includes a semiconductor channel structure including a monocrystalline material. A gate dielectric is over the semiconductor channel structure, the gate dielectric including a high-k dielectric layer on a dipole material layer, and the dipole material layer distinct from the high-k dielectric layer. A gate electrode has a workfunction layer on the high-k dielectric layer, the workfunction layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.

Abstract: Disclosed is a system and method for management of a task across a plurality of processors, wherein the task processing of a plurality of records. The system includes a plurality of processors and an administrator module. Each of the plurality of processors processes a set of records added in a given time interval and the administrator module determines the time interval for a given processor. The administrator module is operable to receive a timestamp detailing a time when the given record was added to the database arrangement; determine a time period in which the plurality of records were added to the database arrangement; determine a time and record threshold for a given processor; and adjust the time interval allocated to each of the plurality of processors according to the time threshold and the record threshold, based on a time-based distribution of records in the database arrangement.

Abstract: Disclosed is a system and method for management of a task across a plurality of processors, wherein the task comprises processing of a plurality of records. The system comprises a plurality of processors and an administrator module. Each of the plurality of processors processes a set of records added in a given time interval and the administrator module determines the time interval for a given processor. The administrator module is operable to receive a timestamp detailing a time when the given record was added to the database arrangement; determine a time period in which the plurality of records were added to the database arrangement; determine a time and record threshold for a given processor; and adjust the time interval allocated to each of the plurality of processors according to the time threshold and the record threshold, based on a time-based distribution of records in the database arrangement.