Abstract: A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.

Abstract: A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.

Abstract: A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.

Abstract: A method for modifying instances of a repeating pattern in an integrated circuit design to correct for perturbations during rendering is described. In the typical embodiment, these corrections are optical proximity corrections that correct for optical effects during the projection of the mask pattern onto the wafer and/or processing effects for example photoresist response and etching effects. The method comprises determining a correction for the repeating pattern based on a first set of tolerances for features of the repeating pattern. Then, the suitability of the corrections is evaluated for instances of the repeating pattern in the integrated circuit design based on a second set of tolerances, which is different from the first set of tolerances. This can be used to preserve much of the hierarchy of the layout data in the corrected, or lithography, data. This can be achieved during the OPC process, thus avoiding the post OPC compaction.