Patents by Inventor Vishwas V. Hardikar

Vishwas V. Hardikar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140199842
    Abstract: In one aspect, a substrate chemical mechanical polishing (CMP) method for substrates is disclosed. The CMP method includes providing a substrate having a surface of silicon and copper such as through silicon via regions containing copper, and polishing the surface with a slurry containing very small silicon nanoparticles (e.g., having an average diameter less than 8 nanometers). CMP systems and slurries for CMP are provided, as are numerous other aspects.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 17, 2014
    Inventors: Vishwas V. Hardikar, Zhihong Wang, David Maxwell Gage, Thomas E. Gartner, III
  • Patent number: 7335288
    Abstract: Methods for electrodeposition of copper on a noble metal layer of a work piece are provided. An exemplary method includes exposing the noble metal layer to an electrodeposition composition. The electrodeposition composition comprises a copper salt, a suppressor, an accelerator and an electrolyte. The electrodeposition of copper on a surface of the noble metal layer is initiated by application of a predetermined current density to the work piece. The electrodeposition of copper is terminated upon the occurrence of a predetermined event.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: February 26, 2008
    Assignee: Novellus Systems, Inc.
    Inventor: Vishwas V. Hardikar
  • Patent number: 7195548
    Abstract: A method and apparatus are provided for post-CMP cleaning of a semiconductor work piece. The method comprises the steps of subjecting the work piece to a first cleaning composition having one of an acidic pH and a basic pH and subjecting the work piece to a second cleaning composition having an acidic pH, if the first cleaning composition has a basic pH and subjecting the work piece to a second cleaning composition having a basic pH, if the first cleaning composition has an acidic pH.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: March 27, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Vishwas V. Hardikar, James A. Schlueter, Guangshun Chen
  • Patent number: 7182673
    Abstract: A method and apparatus are provided for post-CMP cleaning of a semiconductor work piece. The method comprises the steps of subjecting the work piece to a first cleaning composition having one of an acidic pH and a basic pH and subjecting the work piece to a second cleaning composition having an acidic pH, if the first cleaning composition has a basic pH and subjecting the work piece to a second cleaning composition having a basic pH, if the first cleaning composition has an acidic pH.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: February 27, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Vishwas V. Hardikar, James A. Schlueter, Guangshun Chen
  • Patent number: 6869336
    Abstract: Methods and compositions are provided for the chemical mechanical planarization of ruthenium. The method includes polishing the ruthenium layer using a low contact pressure and exposing the ruthenium layer to a planarization composition while polishing. The planarization composition comprises a dispersing medium and a plurality of abrasive particles. The method further includes removing the ruthenium of the ruthenium layer as a ruthenium hydroxide if the pH of the composition is in the range of from about 8 to about 12. The planarization composition may further comprise an oxidizing agent, with the ruthenium removed as a ruthenium hydroxide if the pH of the composition is in the range of from about 2 to about 14. The planarization composition may further comprise a complexing agent, with the ruthenium transformed into an ionic state and removed as a ruthenium complex if the pH of the composition is no greater than about 2.5.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: March 22, 2005
    Assignee: Novellus Systems, Inc.
    Inventor: Vishwas V. Hardikar