Patents by Inventor Viswanathan Nagarajan

Viswanathan Nagarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180191362
    Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
    Type: Application
    Filed: March 1, 2018
    Publication date: July 5, 2018
    Inventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
  • Patent number: 9941893
    Abstract: An ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: April 10, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
  • Publication number: 20170302287
    Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
    Type: Application
    Filed: April 12, 2017
    Publication date: October 19, 2017
    Inventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
  • Patent number: 9748966
    Abstract: A system includes an analog-to-digital converter (ADC) including an ADC input terminal; an ADC output terminal; and analog components configured to convert an analog signal received at the ADC input terminal to a digital signal. The system also includes a histogram estimation circuit coupled to the ADC output terminal and configured to generate information on a plurality of codes generated by the ADC and determine a region defining a range of codes corresponding to an occurrence of an error caused by the analog components of the ADC. The system also includes a dither circuit coupled to the ADC input terminal and configured to introduce a dither in the analog signal to generate a modified analog signal.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 29, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Viswanathan Nagarajan, Srinivas Kumar Reddy Naru, Ratna Kumar Venkata Parupudi
  • Publication number: 20170041013
    Abstract: A system includes an analog-to-digital converter (ADC) including an ADC input terminal; an ADC output terminal; and analog components configured to convert an analog signal received at the ADC input terminal to a digital signal. The system also includes a histogram estimation circuit coupled to the ADC output terminal and configured to generate information on a plurality of codes generated by the ADC and determine a region defining a range of codes corresponding to an occurrence of an error caused by the analog components of the ADC. The system also includes a dither circuit coupled to the ADC input terminal and configured to introduce a dither in the analog signal to generate a modified analog signal.
    Type: Application
    Filed: August 8, 2016
    Publication date: February 9, 2017
    Inventors: Viswanathan NAGARAJAN, Srinivas Kumar Reddy NARU, Ratna Kumar Venkata PARUPUDI
  • Patent number: 8390488
    Abstract: In pipeline analog-to-digital converters (ADCs) the third harmonic can degrade the performance of the ADC, and conventional circuits that attempt to cancel this third harmonic are oftentimes sensitive to process variation, temperature variation, and common mode variations. Here a correction circuit is provided that includes a compensator that adjusts control voltages for MOS capacitors to generally ensures that the difference between the gate-source voltages and threshold voltages of MOS capacitors is generally maintained across variations of process, temperature, and common mode.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: March 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Ganesh Kiran, Visvesvaraya Pentakota, Viswanathan Nagarajan
  • Publication number: 20120056766
    Abstract: In pipeline analog-to-digital converters (ADCs) the third harmonic can degrade the performance of the ADC, and conventional circuits that attempt to cancel this third harmonic are oftentimes sensitive to process variation, temperature variation, and common mode variations. Here a correction circuit is provided that includes a compensator that adjusts control voltages for MOS capacitors to generally ensures that the difference between the gate-source voltages and threshold voltages of MOS capacitors is generally maintained across variations of process, temperature, and common mode.
    Type: Application
    Filed: August 2, 2011
    Publication date: March 8, 2012
    Applicant: Texas Instrumentals Incorporated
    Inventors: Ganesh Kiran, Visveswaraya Pentakota, Viswanathan Nagarajan
  • Patent number: 7961123
    Abstract: A time-interleaved (TI) analog-to-digital converter (ADC) is provided. The TI ADC generally comprises a clock generator, two or more ADCs, adjustable delay elements, and an estimator. The clock generator generates clock signals. Each ADC is associated with at least one of the clock signals so as to sample an input signal that is generally wide-sense stationary at sampling instants, where correlation function exist between samples from a two or more of the ADCs that is a function of the time differences between associated sampling instants. The estimator is coupled to each of the adjustable delay elements and each of the ADCs so as to calculate the correlation function and adjust the adjustable delay elements to account for sampling mismatch between the ADCs based at least in part on the correlation function.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: June 14, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Viswanathan Nagarajan, Sriram Murali, Sthanunathan Ramakrishnan, Visvesvaraya Pentakota, Jaiganesh Balakrishnan
  • Patent number: 7898446
    Abstract: A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a clocking circuit. The first ADC receives an analog input signal and generates a first output and a differentiated output. The second ADC receives the analog input signal and generates a second output. The correction circuit receives the first output, the second output, and the differentiated output and generates a first error signal and a second error signal. The divider receives the first error signal and the second error signal and generates a timing error by dividing the second error signal by the first error signal, and the clocking circuit receives a clock signal and the timing error and generates a plurality of corrected clocking signals, where each of the first and second ADCs receives at least one of the clocking signals.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: March 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Viswanathan Nagarajan, Visvesvaraya A. Pentakota, Jagannathan Venkataraman
  • Publication number: 20110006933
    Abstract: A time-interleaved (TI) analog-to-digital converter (ADC) is provided. The TI ADC generally comprises a clock generator, two or more ADCs, adjustable delay elements, and an estimator. The clock generator generates clock signals. Each ADC is associated with at least one of the clock signals so as to sample an input signal that is generally wide-sense stationary at sampling instants, where correlation function exist between samples from a two or more of the ADCs that is a function of the time differences between associated sampling instants. The estimator is coupled to each of the adjustable delay elements and each of the ADCs so as to calculate the correlation function and adjust the adjustable delay elements to account for sampling mismatch between the ADCs based at least in part on the correlation function.
    Type: Application
    Filed: October 7, 2009
    Publication date: January 13, 2011
    Applicant: Texas Instruments Incorporated
    Inventors: Viswanathan Nagarajan, Sriram Murali, Sthanunathan Ramakrishnan, Visvesvaraya Pentakota, Jaiganesh Balakrishnan
  • Publication number: 20100309033
    Abstract: A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a clocking circuit. The first ADC receives an analog input signal and generates a first output and a differentiated output. The second ADC receives the analog input signal and generates a second output. The correction circuit receives the first output, the second output, and the differentiated output and generates a first error signal and a second error signal. The divider receives the first error signal and the second error signal and generates a timing error by dividing the second error signal by the first error signal, and the clocking circuit receives a clock signal and the timing error and generates a plurality of corrected clocking signals, where each of the first and second ADCs receives at least one of the clocking signals.
    Type: Application
    Filed: July 14, 2009
    Publication date: December 9, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Viswanathan Nagarajan, Visvesvaraya A. Pentakota, Jagannathan Venkataraman