Abstract: A process for forming an electronic component carrier, the electronic carrier having routing layers parallel to an aluminum substrate and vias perpendicular to the aluminum substrate, the process comprising defining routing layers by forming a blocking mask on the aluminum substrate, the blocking mask leaving exposed areas corresponding to the routing layers, carrying out a barrier anodization process on the aluminum substrate to form a surface barrier oxide over the routing layers, removing the blocking mask, providing an upper aluminum layer over the aluminum substrate, defining vias by forming a blocking mask on the upper aluminum layer, the blocking mask covering areas corresponding to the vias, and subjecting both the aluminum substrate and the upper aluminum layer to porous anodization. The barrier oxide defining the routing layer provides reliable masking of the routing layer during porous anodization.

Abstract: A process for forming a multilevel electronic interconnect structure, the electronic interconnect structure having level conductive paths parallel to a substrate and interlevel electrical interconnections perpendicular to the substrate, the process comprising providing a main aluminum layer over the substrate surface, defining level conductive paths by forming a blocking mask on the main aluminum layer, the blocking mask leaving exposed areas corresponding to the level conductive paths, carrying out a barrier anodization process on the main aluminum layer to form a surface barrier oxide over the level conductive paths, removing the blocking mask, providing an upper aluminum layer over the main aluminum layer, defining interlevel interconnections by forming a blocking mask on the upper aluminum layer, the blocking mask covering areas corresponding to the interlevel interconnections, and subjecting the main and upper aluminum layers to porous anodization.

Abstract: A process for forming a multilevel electronic interconnect structure, the electronic interconnect structure having level conductive paths parallel to a substrate and interlevel electrical interconnections perpendicular to the substrate, the process comprising providing a main aluminum layer over the substrate surface, defining level conductive paths by forming a blocking mask on the main aluminum layer, the blocking mask leaving exposed areas corresponding to the level conductive paths, carrying out a barrier anodization process on the main aluminum layer to form a surface barrier oxide over the level conductive paths, removing the blocking mask, providing an upper aluminum layer over the main aluminum layer, defining interlevel interconnections by forming a blocking mask on the upper aluminum layer, the blocking mask covering areas corresponding to the interlevel interconnections, and subjecting the main and upper aluminum layers to porous anodization.