Patents by Inventor Vittorio Cuoco
Vittorio Cuoco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210257977Abstract: Example embodiments relate to power amplifiers with decreased RF return current losses. One embodiment includes a RF power amplifier package that includes a semiconductor die, an input lead, first bondwire connections, second bondwire connections, and a plurality of shields. The semiconductor die includes an RF power transistor that includes output bond pads, input bond pads, a plurality of input fingers, and a plurality of output fingers. Further, each shield of the plurality of shields is arranged in between a respective input finger of the plurality of input fingers and a respective output finger of the plurality of output fingers and extending along with said respective input finger and output finger. In addition, each shield of the plurality of shields is connected to a ground terminal of the RF power transistor. The input fingers, output fingers, and shields are formed using a metal layer stack of multiple metal layers.Type: ApplicationFiled: September 3, 2019Publication date: August 19, 2021Inventors: Vittorio Cuoco, Jos Van Der Zanden, Yi Zhu, Iouri Volokhine
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Patent number: 10685927Abstract: A packaged RF power amplifier comprises an output network coupled to the output of a RF power transistor, which output network comprises a plurality of first bondwires extending along a first direction between the output of transistor and an output lead of the package, a series connection of a second inductor and a first capacitor between the output of the RF power transistor and ground, and a series connection of a third inductor and a second capacitor connected in between ground and the junction between the second inductor and the first capacitor. The first and second capacitors are integrated on a single passive die and the third inductor comprises a first part and a second part connected in series, wherein the first part extends at least partially along the first direction, and wherein the second part extends at least partially in a direction opposite to the first direction.Type: GrantFiled: August 23, 2017Date of Patent: June 16, 2020Assignee: Ampleon Netherlands B.V.Inventors: Johannes Adrianus Maria De Boet, Yi Zhu, Yuri Volokhine, Vittorio Cuoco, Albertus Gerardus Wilhelmus Philipus Van Zuijlen, Iordan Konstantlnov Sveshtarov, Josephus Henricus Bartholomeus Van der Zanden
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Patent number: 10553543Abstract: An integrated circuit package is provided. The integrated circuit package comprises a first and second guard bond wire. The first guard bond wire has a first and second end coupled to ground. The second guard bond wire has a first and second end coupled to ground. The integrated circuit package further comprises a die. The die is mounted between the first and second guard bond wires such that the first and second guard bond wires distort a magnetic field between at least an input terminal and an output terminal of the die.Type: GrantFiled: May 12, 2016Date of Patent: February 4, 2020Assignee: Ampleon Netherlands B.V.Inventors: Vittorio Cuoco, Youri Volkhine, Yi Zhu, Josephus Van Der Zanden, Anna Walesieniuk
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Publication number: 20190229077Abstract: A packaged RF power amplifier comprises an output network coupled to the output of a RF power transistor, which output network comprises a plurality of first bondwires extending along a first direction between the output of transistor and an output lead of the package, a series connection of a second inductor and a first capacitor between the output of the RF power transistor and ground, and a series connection of a third inductor and a second capacitor connected in between ground and the junction between the second inductor and the first capacitor. The first and second capacitors are integrated on a single passive die and the third inductor comprises a first part and a second part connected in series, wherein the first part extends at least partially along the first direction, and wherein the second part extends at least partially in a direction opposite to the first direction.Type: ApplicationFiled: August 23, 2017Publication date: July 25, 2019Inventors: Johannes Adrianus Maria De Boet, Yi Zhu, Yuri Volokhine, Vittorio Cuoco, Albertus Gerardus Wihelmusi Van Zuijlen, Jordan Konstantlnov Sveshtarov
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Publication number: 20190006286Abstract: An integrated circuit package is provided. The integrated circuit package comprises a first and second guard bond wire. The first guard bond wire has a first and second end coupled to ground. The second guard bond wire has a first and second end coupled to ground. The integrated circuit package further comprises a die. The die is mounted between the first and second guard bond wires such that the first and second guard bond wires distort a magnetic field between at least an input terminal and an output terminal of the die.Type: ApplicationFiled: May 12, 2016Publication date: January 3, 2019Inventors: Vittorio CUOCO, Youri VOLKHINE, Yi ZHU, Josephus VAN DER ZANDEN, Anna WALESIENIUK
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Patent number: 9928954Abstract: A bond-wire transformer for an RF device is described. The primary and secondary circuits of the bond-wire transformer are formed using loops formed with a pair of normal profile and low profile bond-wires. This results in improved efficiency and higher power operation.Type: GrantFiled: August 7, 2015Date of Patent: March 27, 2018Assignee: Ampleon Netherlands B.V.Inventor: Vittorio Cuoco
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Patent number: 9627301Abstract: An integrated circuit arrangement includes a flange, a transistor die, and a first conducting element defining a lead. The flange includes a conducting material and the transistor die is disposed on a surface of the flange. The first conducting element is electrically connected to the transistor die via connecting elements to allow current flow from the transistor die. The flange defines return current paths allowing the current flow via the connecting elements and the lead to return to the transistor die. The flange includes one or more reduced thickness portions that are configured to limit the return current paths and control current flow passing through the flange to the transistor die.Type: GrantFiled: May 3, 2015Date of Patent: April 18, 2017Assignee: Ampleon Netherlands B.V.Inventor: Vittorio Cuoco
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Patent number: 9413308Abstract: In RF power transistors, the current distribution along edges of the transistor die may be uneven leading to a loss in efficiency and in the output power obtained, resulting in degradation in performance. When multiple parallel dies are placed in a package, distribution effects along the vertical dimension of the dies are more pronounced. A RF power device (600) for amplifying RF signals is disclosed which modifies the impedance of a portion of the respective one of the input lead and the output lead and redistributes the current flow at an edge of the transistor die.Type: GrantFiled: June 27, 2014Date of Patent: August 9, 2016Assignee: Ampleon Netherlands B.V.Inventors: Josephus van der Zanden, Vittorio Cuoco, Rob Mathijs Heeres
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Publication number: 20160064140Abstract: A bond-wire transformer for an RF device is described. The primary and secondary circuits of the bond-wire transformer are formed using loops formed with a pair of normal profile and low profile bond-wires. This results in improved efficiency and higher power operation.Type: ApplicationFiled: August 7, 2015Publication date: March 3, 2016Inventor: Vittorio Cuoco
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Patent number: 9209118Abstract: An integrated circuit arrangement comprising a substrate and a flange disposed on top of the substrate. The flange comprises a cantilever portion configured to project over the substrate. A die disposed on top of the flange. A first output terminal disposed on the substrate. A first lead configured to provide for an electrical connection between the die and the first output terminal. A first electrically conducting member configured to provide at least part of a current return path between the substrate and the die and arranged to bridge a gap between the cantilever portion and the substrate. The first electrically conducting member is disposed between the die and the first output terminal and is configured to enable electrical current to flow from the substrate to the cantilever portion of the flange.Type: GrantFiled: March 16, 2015Date of Patent: December 8, 2015Assignee: NXP, B.V.Inventors: Vittorio Cuoco, Albert van Zuijlen, Josephus van der Zanden
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Publication number: 20150348883Abstract: An integrated circuit arrangement comprising: a flange, the flange comprising conducting material; a transistor die disposed on the surface of the flange; a first conducting element, the first conducting element being electrically connected to the transistor die to allow current flow from the transistor die; wherein the flange comprises one or more reduced thickness portions, the one or more reduced thickness portions being configured to control current flow passing through the flange to the transistor die.Type: ApplicationFiled: May 3, 2015Publication date: December 3, 2015Inventor: Vittorio Cuoco
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Patent number: 9190970Abstract: An integrated power amplifier circuit is disclosed. The circuit comprises: first and second amplifiers fabricated on one or more dies, the one or more dies being mounted on a support structure; a first set of one or more connection elements connected to the first amplifier and passing above a portion of the support structure; and a second set of one or more connection elements connected to the second amplifier and passing above a portion of the support structure. The support structure comprises at least one void, at least a portion of the at least one void being positioned directly underneath at least one of the first and second sets of one or more connection elements.Type: GrantFiled: November 14, 2013Date of Patent: November 17, 2015Assignee: NXP B.V.Inventors: Vittorio Cuoco, Josephus Henricus Bartholomeus van der Zanden, Albert Gerardus Wilhelmus Philipus van Zuijlen
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Publication number: 20150270198Abstract: An integrated circuit arrangement comprising a substrate and a flange disposed on top of the substrate. The flange comprises a cantilever portion configured to project over the substrate. A die disposed on top of the flange. A first output terminal disposed on the substrate. A first lead configured to provide for an electrical connection between the die and the first output terminal. A first electrically conducting member configured to provide at least part of a current return path between the substrate and the die and arranged to bridge a gap between the cantilever portion and the substrate. The first electrically conducting member is disposed between the die and the first output terminal and is configured to enable electrical current to flow from the substrate to the cantilever portion of the flange.Type: ApplicationFiled: March 16, 2015Publication date: September 24, 2015Inventors: Vittorio Cuoco, Albert van Zuijlen, Josephus van der Zanden
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Patent number: 9007129Abstract: The disclosure relates to an amplifier device comprising an integrated circuit die (701a; 701b) having a first amplifier (702a; 702b) and a second amplifier. A Doherty amplifier may be implemented in accordance with the present invention. The amplifier device also comprises a first connector (706a; 706b) having a first end coupled to the first amplifier and a second end for coupling with a circuit board (718a; 718b), a second connector (708a; 708b) having a first end coupled to the second amplifier (704a; 704b) and a second end for coupling with a circuit board (718a; 718b), a shielding member (710a; 710b) having a first end coupled to the integrated circuit die (701a; 701b) and a second end for coupling with a circuit board (718a; 718b), the shielding member (710a; 710b) situated at least partially between the second connector and the first connector (706a; 706b) and a capacitor. The capacitor has a first plate and a second plate.Type: GrantFiled: December 17, 2013Date of Patent: April 14, 2015Assignee: NXP, B.V.Inventors: Albert Gerardus Wilhelmus Philipus van Zuijlen, Vittorio Cuoco, Josephus Henricus Bartholomeus van der Zanden
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Patent number: 8981433Abstract: A compensation network for a radiofrequency transistor is disclosed. The compensation network comprises first and second bonding bars for coupling to a first terminal of the RF transistor and a compensation capacitor respectively; one or more bond wires coupling the first and second bonding bars together; and a compensation capacitor formed from a first set of conductive elements coupled to the second bonding bar, the first set of conductive elements interdigitating with a second set of conductive elements coupled to a second terminal of the RF transistor.Type: GrantFiled: November 23, 2011Date of Patent: March 17, 2015Assignee: NXP, B.V.Inventors: Lukas Frederik Tiemeijer, Vittorio Cuoco, Rob Mathijs Heeres, Jan Anne van Steenwijk, Marnix Bernard Willemsen, Josephus Henricus Bartholomeus van der Zanden
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Publication number: 20150028955Abstract: In RF power transistors, the current distribution along edges of the transistor die may be uneven leading to a loss in efficiency and in the output power obtained, resulting in degradation in performance. When multiple parallel dies are placed in a package, distribution effects along the vertical dimension of the dies are more pronounced. A RF power device (600) for amplifying RF signals is disclosed which modifies the impedance of a portion of the respective one of the input lead and the output lead and redistributes the current flow at an edge of the transistor die.Type: ApplicationFiled: June 27, 2014Publication date: January 29, 2015Inventors: Josephus van der Zanden, Vittorio Cuoco, Rob Mathijs Heeres
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Publication number: 20140167858Abstract: The disclosure relates to an amplifier device comprising an integrated circuit die (701a; 701b) having a first amplifier (702a; 702b) and a second amplifier. A Doherty amplifier may be implemented in accordance with the present invention. The amplifier device also comprises a first connector (706a; 706b) having a first end coupled to the first amplifier and a second end for coupling with a circuit board (718a; 718b), a second connector (708a; 708b) having a first end coupled to the second amplifier (704a; 704b) and a second end for coupling with a circuit board (718a; 718b), a shielding member (710a; 710b) having a first end coupled to the integrated circuit die (701a; 701b) and a second end for coupling with a circuit board (718a; 718b), the shielding member (710a; 710b) situated at least partially between the second connector and the first connector (706a; 706b) and a capacitor. The capacitor has a first plate and a second plate.Type: ApplicationFiled: December 17, 2013Publication date: June 19, 2014Applicant: NXP B.V.Inventors: Albert Gerardus Wilhelmus Philipus van Zuijlen, Vittorio Cuoco, Josephus Henricus Bartholomeus van der Zanden
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Publication number: 20140132353Abstract: An integrated power amplifier circuit is disclosed. The circuit comprises: first and second amplifiers fabricated on one or more dies, the one or more dies being mounted on a support structure; a first set of one or more connection elements connected to the first amplifier and passing above a portion of the support structure; and a second set of one or more connection elements connected to the second amplifier and passing above a portion of the support structure. The support structure comprises at least one void, at least a portion of the at least one void being positioned directly underneath at least one of the first and second sets of one or more connection elements.Type: ApplicationFiled: November 14, 2013Publication date: May 15, 2014Applicant: NXP B.V.Inventors: Vittorio Cuoco, Josephus Henricus Bartholomeus van der Zanden, Albert Gerardus Wilhelmus Philipus van Zuijlen
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Publication number: 20120132969Abstract: A compensation network for a radiofrequency transistor is disclosed. The compensation network comprises first and second bonding bars for coupling to a first terminal of the RF transistor and a compensation capacitor respectively; one or more bond wires coupling the first and second bonding bars together; and a compensation capacitor formed from a first set of conductive elements coupled to the second bonding bar, the first set of conductive elements interdigitating with a second set of conductive elements coupled to a second terminal of the RF transistor.Type: ApplicationFiled: November 23, 2011Publication date: May 31, 2012Applicant: NXP B.V.Inventors: Lukas Frederik Tiemeijer, Vittorio Cuoco, Rob Mathijs Heeres, Jan Anne van Steenwijk, Marnix Bernard Willemsen, Josephus Henricus Bartholomeus van der Zanden