Patents by Inventor Vivek ANGOTH

Vivek ANGOTH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PAGE MAP RENUMBERING TO REDUCE ERROR CORRECTION FAILURES AND IMPROVE PROGRAM TIME UNIFORMITY
    Publication number: 20230044991
    Abstract: Systems, apparatuses and methods may provide for technology that detects a request to program a NAND memory containing a plurality of dies and programs the NAND memory on a stripe-by-stripe basis, wherein each stripe spans the plurality of dies and includes multiple types of pages. The multiple types of pages may reduce program time variability across the stripes and reduce the error susceptibility of the NAND memory.
    Type: Application
    Filed: August 4, 2021
    Publication date: February 9, 2023
    Inventors: Shantanu Rajwade, Kartik Ganapathi, Rohit Shenoy, Kristopher Gaewsky, MarkAnthony Golez, Vivek Angoth, Pranav Kalavade, Sarvesh Gangadhar
  • DYNAMIC PROGRAM SUSPEND DISABLE FOR RANDOM WRITE SSD WORKLOAD
    Publication number: 20210247937
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to NAND-based storage media that includes a plurality of NAND devices, determine if a current workload for a particular NAND device of the plurality of NAND devices is a random write workload, and, if so determined, disable a program suspend operation for only the particular NAND device. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 27, 2021
    Publication date: August 12, 2021
    Applicant: Intel Corporation
    Inventors: Vivek Angoth, David Carlton, Sarvesh Gangadhar, MarkAnthony Golez, David J. Pelster, Neelesh Vemula
  • Read performance on a SATA storage device behind a host bus adapter
    Patent number: 10452574
    Abstract: Examples may include a storage device coupled to a host bus adapter and a SATA controller over a SATA interface. The storage device includes a memory and a storage device controller. The storage device controller includes a collision detector and counter component to detect and count collisions on the SATA interface for a period of time; and a bus limiter component to detect a type of workload on the SATA interface, and when the detected workload is only read commands and a number of detected collisions is less than a detected collision threshold during the period of time, to set a limit on a maximum number of commands sent by the host bus adapter to the storage device controller over the SATA interface.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Vivek Angoth, Hung Huynh, Daniel McLeran
  • READ PERFORMANCE ON A SATA STORAGE DEVICE BEHIND A HOST BUS ADAPTER
    Publication number: 20190042493
    Abstract: Examples may include a storage device coupled to a host bus adapter and a SATA controller over a SATA interface. The storage device includes a memory and a storage device controller. The storage device controller includes a collision detector and counter component to detect and count collisions on the SATA interface for a period of time; and a bus limiter component to detect a type of workload on the SATA interface, and when the detected workload is only read commands and a number of detected collisions is less than a detected collision threshold during the period of time, to set a limit on a maximum number of commands sent by the host bus adapter to the storage device controller over the SATA interface.
    Type: Application
    Filed: July 26, 2018
    Publication date: February 7, 2019
    Inventors: Vivek ANGOTH, Hung HUYNH, Daniel MCLERAN