Patents by Inventor Vivek Chickermane
Vivek Chickermane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8271226Abstract: A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.Type: GrantFiled: June 26, 2008Date of Patent: September 18, 2012Assignee: Cadence Design Systems, Inc.Inventors: Krishna Chakravadhanula, Patrick Gallagher, Vivek Chickermane, Steven L. Gregor, Puneet Arora
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Patent number: 8001433Abstract: In a circuit adapted for scan testing, a first set of connections configures the circuit elements into power domains with separate power-level controls, and a second set of connections configures the circuit elements to form scan segments for loading values into circuit elements from input ends of the scan segments and unloading values from circuit elements at output ends of the scan segments. A decompressor circuit receives a decompressor input and is operatively connected to the scan-segment input ends, and a compressor circuit is operatively connected to the scan segment output ends and generates a compressor output. Isolation circuits at scan-segment exits set values for scan segments at scan-segment exits when a corresponding independent power domain is in a power-off state.Type: GrantFiled: December 30, 2008Date of Patent: August 16, 2011Assignee: Cadence Design Systems, Inc.Inventors: Sandeep Bhatia, Patrick Gallagher, Brian Foutz, Vivek Chickermane
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Patent number: 7979764Abstract: A method for testing integrated circuits is provided. The method provides for incorporating compression and decompression logic into each sub-component of an integrated circuit, developing test modes that target different sub-components of the integrated circuit, selecting one of the test modes, applying a test pattern to one or more sub-components of the integrated circuit targeted by the one test mode, comparing a response from application of the test pattern to a known good response, and diagnosing the response to determine which part of the one or more sub-components targeted by the one test mode failed when the response does not match the known good response.Type: GrantFiled: November 1, 2007Date of Patent: July 12, 2011Assignee: Cadence Design Systems, Inc.Inventors: Brian Foutz, Patrick Gallagher, Vivek Chickermane, Carl Barnhart
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Patent number: 7944285Abstract: An integrated circuit is provided that comprises a power switch that includes a control terminal and that is coupled between a power source node and a power sink node; first data storage circuit includes a data storage input and a data storage output, wherein the data storage output is coupled to the power switch control terminal; and a second data storage circuit includes a data storage input and a data storage output, wherein the data storage input is coupled to the power sink node.Type: GrantFiled: April 9, 2008Date of Patent: May 17, 2011Assignee: Cadence Design Systems, Inc.Inventors: Senthil Arasu Thirunavukarasu, Bambuda Chen Chien Leung, Shaleen Bhabu, Vivek Chickermane
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Patent number: 7926012Abstract: A method is provided to improve the usability of Design-For-Testability Synthesis (DFTS) tools and to increase the design process productivity. The method comprises receiving a list of testability and design impact analysis functions, to be performed on the circuit, also referred to as a device under test (DUT). The impact analysis leads to the creation of logical transformations, which can be selected by a user with one or more available transformation methods from a list including, but not limited to, boundary scan test logic insertion, scan test logic insertion, memory BIST (built-in-self-test) logic insertion, and logic BIST logic insertion, and scan test data compression insertion logic insertion.Type: GrantFiled: December 6, 2007Date of Patent: April 12, 2011Assignee: Cadence Design Systems, Inc.Inventors: Nitin Parimi, Patrick Gallagher, Brian Foutz, Vivek Chickermane
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Patent number: 7886263Abstract: State retention cells of a test circuit embedded in an electrical circuit are interconnected to form one or more scan chains. The scan chains are interconnected so that unknown states, or X-states, are shifted through the scan chains in an order other than the order in which the states were captured by the state retention cells of the scan chain. Such reordering of response states in individual scan chains may be used to align the X-states across multiple scan chains to achieve higher test compression scan register circuit testing.Type: GrantFiled: December 10, 2007Date of Patent: February 8, 2011Assignee: Cadence Design Systems, Inc.Inventors: Senthil Arasu Thirunavukarasu, Vivek Chickermane, Shaleen Bhabu
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Patent number: 7877715Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.Type: GrantFiled: March 28, 2008Date of Patent: January 25, 2011Assignee: Cadence Design Systems, Inc.Inventors: Senthil Arasu Thirunavukarasu, Shaleen Bhabu, Vivek Chickermane
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Patent number: 7779381Abstract: In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power domain or portion of a power domain, to a test mode. Thereby only those portions of the circuit which need to be powered up in a particular test mode are powered up both in the design (simulation) phase and in the actual testing. This conserves power usage during actual testing as against powering up all portions of the circuit, which is not desirable during the testing of the circuit after manufacture. This ensures that the power conditions required to excite and observe any circuit faults during testing exist for the power conditions that are applied during, for instance, manufacturing testing.Type: GrantFiled: September 11, 2006Date of Patent: August 17, 2010Assignee: Cadence Design Systems, Inc.Inventors: Vivek Chickermane, James Sage, Patrick Gallagher, Xiaochuan Yuan
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Patent number: 7739629Abstract: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.Type: GrantFiled: October 30, 2006Date of Patent: June 15, 2010Assignee: Cadence Design Systems, Inc.Inventors: Qi Wang, Ankur Gupta, Pinhong Chen, Christina Chu, Manish Pandey, Huan-Chih Tsai, Sandeep Bhatia, Yonghao Chen, Steven Sharp, Vivek Chickermane, Patrick Gallagher
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Patent number: 7693676Abstract: Low power design is a critical concern and metric for integrated circuits. During scan based manufacturing test, electric power dissipation becomes even more critical as the chip may not have been designed to tolerate excessive switching during scan test. Excessive electric power dissipation during scan test can result in excessive voltage variations, reduced noise margins and other signal integrity issues which could invalidate the test or may lead to premature chip failure. Power dissipation during test is minimized by selecting particular values for the unused care-bits in values of the test vectors on a probabilistic basis to minimize switching, while preserving test vector quality.Type: GrantFiled: February 9, 2007Date of Patent: April 6, 2010Assignee: Cadence Design Systems, Inc.Inventors: Brion L. Keller, Vivek Chickermane, Sandeep Bhatia
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Publication number: 20090326854Abstract: A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.Type: ApplicationFiled: June 26, 2008Publication date: December 31, 2009Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Krishna CHAKRAVADHANULA, Patrick Gallagher, Vivek Chickermane, Steven L. Gregor, Puneet Arora
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Publication number: 20090119559Abstract: A method for testing integrated circuits is provided. The method provides for incorporating compression and decompression logic into each sub-component of an integrated circuit, developing test modes that target different sub-components of the integrated circuit, selecting one of the test modes, applying a test pattern to one or more sub-components of the integrated circuit targeted by the one test mode, comparing a response from application of the test pattern to a known good response, and diagnosing the response to determine which part of the one or more sub-components targeted by the one test mode failed when the response does not match the known good response.Type: ApplicationFiled: November 1, 2007Publication date: May 7, 2009Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Brian Foutz, Patrick Gallagher, Vivek Chickermane, Carl Barnhart
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Publication number: 20080071513Abstract: In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power domain or portion of a power domain, to a test mode. Thereby only those portions of the circuit which need to be powered up in a particular test mode are powered up both in the design (simulation) phase and in the actual testing. This conserves power usage during actual testing as against powering up all portions of the circuit, which is not desirable during the testing of the circuit after manufacture. This ensures that the power conditions required to excite and observe any circuit faults during testing exist for the power conditions that are applied during, for instance, manufacturing testing.Type: ApplicationFiled: September 11, 2006Publication date: March 20, 2008Applicant: Cadence Design Systems, Inc.Inventors: Vivek Chickermane, James Sage, Patrick Gallagher, Xiaochuan Yuan
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Publication number: 20070245285Abstract: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.Type: ApplicationFiled: October 30, 2006Publication date: October 18, 2007Inventors: Qi Wang, Ankur Gupta, Pinhong Chen, Christina Chu, Manish Pandey, Huan-Chih Tsai, Sandeep Bhatia, Yonghao Chen, Steven Sharp, Vivek Chickermane, Patrick Gallagher