Patents by Inventor Vivek Gopalan

Vivek Gopalan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for forming buried conductive line and structure of buried conductive line
    Patent number: 9653401
    Abstract: A method for forming a buried conductive line is described. A substrate having a trench therein and a contact area thereon is provided, wherein the trench has an end portion in the contact area and a conductive layer is filled in the trench. A mask layer is formed covering the conductive layer in the contact area. The conductive layer is etched back using the mask layer as a mask.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: May 16, 2017
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Vivek Gopalan
  • Memory process
    Patent number: 9147604
    Abstract: A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: September 29, 2015
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Vivek Gopalan, Robert Kerr, Hung-Ming Tsai
  • Memory process and memory structure made thereby
    Patent number: 9123784
    Abstract: A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: September 1, 2015
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Vivek Gopalan, Robert Kerr, Hung-Ming Tsai
  • MEMORY PROCESS
    Publication number: 20150111377
    Abstract: A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.
    Type: Application
    Filed: December 24, 2014
    Publication date: April 23, 2015
    Inventors: Vivek Gopalan, Robert Kerr, Hung-Ming Tsai
  • MEMORY PROCESS AND MEMORY STRUCTURE MADE THEREBY
    Publication number: 20140054794
    Abstract: A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Vivek Gopalan, Robert Kerr, Hung-Ming Tsai
  • METHOD FOR FORMING BURIED CONDUCTIVE LINE AND STRUCTURE OF BURIED CONDUCTIVE LINE
    Publication number: 20130270708
    Abstract: A method for forming a buried conductive line is described. A substrate having a trench therein and a contact area thereon is provided, wherein the trench has an end portion in the contact area and a conductive layer is filled in the trench. A mask layer is formed covering the conductive layer in the contact area. The conductive layer is etched back using the mask layer as a mask.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 17, 2013
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: Vivek Gopalan