Abstract: A deinterlacing apparatus includes a buffer to receive a plurality of consecutive fields of an interlaced video and a field combination module coupled to the buffer to deinterlace the interlaced video in accordance with cadence of the interlaced video. The deinterlacing apparatus also includes a cadence detection module to detect the cadence by (1) causing each of the fields to be combined with its preceding field into a frame and with its subsequent field into another frame to obtain a plurality of combined frames, (2) determining a comb factor of each of the combined frames to obtain a sequence of comb factors of the combined frames, and (3) determining if the sequence of comb factors of the combined frames follows a pre-determined repeating pattern. A cadence detection method is also described.

Abstract: Various embodiments of the present disclosure provide techniques for performing video denoising (VDN). An adaptive noise threshold is dynamically determined and used to distinguish between frame to frame differences in pixel values that relate to image motion from those differences that relate to noise. The disclosed techniques enable the noise threshold to be continuously updated, for example as frequently as once per frame, so that the noise threshold may closely track to varying levels of noise in the input video data. The techniques may be implemented in, for example, a video format conversion apparatus. Advantageously, the techniques may be incorporated in programmable logic devices (PLD's) or Field Programmable Gate Arrays (FPGA's) configurable to perform video format conversion, while adding only modest additional computational demands on the apparatus.

Abstract: A deinterlacing apparatus includes a buffer to receive a plurality of consecutive fields of an interlaced video and a field combination module coupled to the buffer to deinterlace the interlaced video in accordance with cadence of the interlaced video. The deinterlacing apparatus also includes a cadence detection module to detect the cadence by (1) causing each of the fields to be combined with its preceding field into a frame and with its subsequent field into another frame to obtain a plurality of combined frames, (2) determining a comb factor of each of the combined frames to obtain a sequence of comb factors of the combined frames, and (3) determining if the sequence of comb factors of the combined frames follows a pre-determined repeating pattern. A cadence detection method is also described.

Abstract: Various embodiments of the present disclosure provide techniques for performing video denoising (VDN). An adaptive noise threshold is dynamically determined and used to distinguish between frame to frame differences in pixel values that relate to image motion from those differences that relate to noise. The disclosed techniques enable the noise threshold to be continuously updated, for example as frequently as once per frame, so that the noise threshold may closely track to varying levels of noise in the input video data. The techniques may be implemented in, for example, a video format conversion apparatus. Advantageously, the techniques may be incorporated in programmable logic devices (PLD's) or Field Programmable Gate Arrays (FPGA's) configurable to perform video format conversion, while adding only modest additional computational demands on the apparatus.

Abstract: Various embodiments of the present disclosure provide techniques for performing video denoising (VDN). An adaptive noise threshold is dynamically determined and used to distinguish between frame to frame differences in pixel values that relate to image motion from those differences that relate to noise. The disclosed techniques enable the noise threshold to be continuously updated, for example as frequently as once per frame, so that the noise threshold may closely track to varying levels of noise in the input video data. The techniques may be implemented in, for example, a video format conversion apparatus. Advantageously, the techniques may be incorporated in programmable logic devices (PLD's) or Field Programmable Gate Arrays (FPGA's) configurable to perform video format conversion, while adding only modest additional computational demands on the apparatus.

Abstract: A method of estimating the interlacing mode used in a series of video frames presented as a sequence of fields is described. In one implementation, the method includes calculating a metric indicative of the difference between a current field of the sequence and a previous field of the sequence and determining from the metric so calculated the most likely type of the current field by reference to a Hidden Markov Model.