Abstract: A device for a system on a chip (SOC), the device includes: a comparator that includes a first input port, a second input port, and an output port. A first input signal and a second input signal are split into N bit pairs that include one bit from the first input signal and one bit from the second input signal. The comparator is configured so a mismatch between the first input signal and the second input signal causes an output signal to assume a first expected state. The device further comprises a test controller to perform a first operability test by mismatching the N bit pairs and verifying that the output signal assumes the first expected state.

Abstract: The present invention provides an instrument assembly that is expandable in steps for providing precise measurement of bone gap and distraction of bone in a controlled manner. It discloses a tool performing expandable Bi-Surface Mechanism to expand a bi-compartmental structure. The disclosed system is equipped with two active surfaces (Bottom base and a top plate) between which a force is applied to move the surfaces in relation to each other for providing precise measurement of bone gap and distraction of bone in a controlled manner. Additionally, the control mechanism of the present invention includes applying direct and/or measured/graduated separation force between the two surfaces and able to deliver haptic and sensor-based feedback to the surgeon for the critical ligament tensioning and balancing aspects of the procedure.

Abstract: Techniques for supporting invocations of the RDTSC (Read Time-Stamp Counter) instruction, or equivalents thereof, by guest program code running within a virtual machine (VM), including guest program code running within a secure hardware enclave of the VM, are provided. In one set of embodiments, a hypervisor can activate time virtualization heuristics for the VM, where the time virtualization heuristics cause accelerated delivery of system clock timer interrupts to a guest operating system (OS) of the VM. The hypervisor can further determine a scaling factor to be applied to timestamps generated by one or more physical CPUs, where the timestamps are generated in response to invocations of a CPU instruction made by guest program code running within the VM, and where the scaling factor is based on the activated time virtualization heuristics. The hypervisor can then program the scaling factor into the one or more physical CPUs.

Abstract: A method of migrating a virtual machine having a virtual device that is backed by direct passthrough hardware, from a source host to a destination host, includes the steps of determining whether or not the destination host has direct passthrough hardware that can back the virtual device, and upon determining that the destination host has direct passthrough hardware that can back the virtual device, determining if a version of the direct passthrough hardware at the source host matches a version of the direct passthrough hardware at the destination host. If the versions do not match, the steps further include quiescing the virtual device, deleting data structures relating to the virtual device, and then migrating the virtual machine from the source host to the destination host. If the versions match, the virtual machine is migrated without quiescing the virtual device and without deleting the data structures relating to the virtual device.

Abstract: A virtual machine (VM) has direct access to an I/O device having physical and virtual functions and a mailbox register, and includes a guest driver for controlling the virtual functions. The VM runs on system software that includes a physical driver for controlling the physical function (PF) and maintains VM page tables, which include an entry that references a memory space into which the mailbox register is mapped. The system software registers a callback function with the physical driver, which the physical driver invokes upon receiving a trigger for communication with the guest driver. In response, the system software alters the page tables so that access to the mailbox register causes a PF intercept, and the callback function handles the communication with the guest driver. After completion of the communication, the system software alters the page tables so that access to the mailbox register does not cause a PF intercept.

Abstract: Disclosed are aspects of a Precision Time Protocol (PTP) implementation in a virtualized environment. A PTP daemon is executed in a VM that publishes clock parameters generated from a NIC providing a PTP stack to a shared memory space. Other VM's can obtain the clock parameters and synchronize clocks using a PTP daemon executed on the VM.

Abstract: Techniques for enabling live migration of VMs with passthrough PCI devices are provided. In one set of embodiments, a hypervisor of a host system can create a copy of a DMA buffer used by a VM of the host system and a passthrough PCI device of the VM. The hypervisor can further designate one of the DMA buffer or the copy of the DMA buffer as a vCPU buffer that is accessible by the VM, and designate the other of the DMA buffer or the copy of the DMA buffer as a device buffer that is accessible by the passthrough PCI device. The hypervisor can then synchronize the vCPU buffer and the device buffer with each other as the VM and passthrough PCI device interact with their respective buffers, and as part of the synchronization can intercept DMA work requests submitted by the VM/completed by the passthrough PCI device.

Abstract: Techniques for enabling live migration of VMs with passthrough PCI devices are provided. In one set of embodiments, a hypervisor of a host system can create a copy of a DMA buffer used by a VM of the host system and a passthrough PCI device of the VM. The hypervisor can further designate one of the DMA buffer or the copy of the DMA buffer as a vCPU buffer that is accessible by the VM, and designate the other of the DMA buffer or the copy of the DMA buffer as a device buffer that is accessible by the passthrough PCI device. The hypervisor can then synchronize the vCPU buffer and the device buffer with each other as the VM and passthrough PCI device interact with their respective buffers, and as part of the synchronization can intercept DMA work requests submitted by the VM/completed by the passthrough PCI device.

Abstract: Techniques for enabling live migration of VMs with passthrough PCI devices are provided. In one set of embodiments, a hypervisor of a host system can create a copy of a DMA buffer used by a VM of the host system and a passthrough PCI device of the VM. The hypervisor can further designate one of the DMA buffer or the copy of the DMA buffer as a vCPU buffer that is accessible by the VM, and designate the other of the DMA buffer or the copy of the DMA buffer as a device buffer that is accessible by the passthrough PCI device. The hypervisor can then synchronize the vCPU buffer and the device buffer with each other as the VM and passthrough PCI device interact with their respective buffers, and as part of the synchronization can intercept DMA work requests submitted by the VM/completed by the passthrough PCI device.

Abstract: Probes are employed to inject errors into code. In response to a function-entry trigger event, a probe writes a predefined test value to a return value register. The probe then cause function execution to be skipped such that the test value is returned in lieu of the value which would otherwise be returned by the function. Behavior after the error is injected may then be observed, data collected, etc. such that undesired behavior (e.g., crashes) can be identified and/or corrected. In an alternative embodiment, the probe which is triggered may write a test value to a given memory address.

Abstract: Probes are employed to inject errors into code. In response to a function-entry trigger event, a probe writes a predefined test value to a return value register. The probe then cause function execution to be skipped such that the test value is returned in lieu of the value which would otherwise be returned by the function. Behavior after the error is injected may then be observed, data collected, etc. such that undesired behavior (e.g., crashes) can be identified and/or corrected. In an alternative embodiment, the probe which is triggered may write a test value to a given memory address.

Abstract: Apparatus having corresponding methods and non-transitory computer-readable media comprise: a wireless local-area network (WLAN) module comprising a receiver configured to receive a WLAN signal into the WLAN module; a transmitter; and a loopback controller configured to selectively loop back the WLAN signal to the transmitter, wherein the transmitter is configured to transmit the looped-back WLAN signal from the WLAN module.

Abstract: An interface input has an input circuit adapted to receive input signal levels higher than a maximum signal level that a host circuitry's electronic components can reliably handle. The input circuit shifts the level of the input signal to a desired signal level. A keeper circuit is coupled to the input circuit and maintains trigger levels of the shifted signals consistent with the input signal level.

Abstract: A digital radio frequency (RF) modulator provides modulation for base-band TV signals. The RF modulator provides direct conversion of digital base-band audio and video signals to a desired RF channel frequency, without any analog up conversion. The RF modulator includes an audio module, a video module, and a RF converter. The audio module includes a pre-emphasis filter, a multi-stage audio interpolator and a complex frequency modulator to generate frequency modulated (FM) audio signals. The video module includes a complex VSB filter, a group-delay compensation filter and some processing logic to generate a filtered output video signal. The RF converter includes a complex adder, a complex multiplier and a RF interpolator to construct the base band TV signals and to shift the base band TV signals in a frequency domain to the desired RF channel frequency. The exponential video carrier is generated at baseband and has a frequency whose value is in the range of +/?13.5 MHz.

Abstract: A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.

Abstract: A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a second signal level. Electronic components of the first and second stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter and the second stage level shifter prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.

Abstract: A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at least on of either the pull up or pull down circuit. The timing circuit controls a time of application of an input signal to at least one of either the pull up or pull down circuit preventing a terminal to terminal signal level experienced by the electronic components exceeding the reliability limits.

Abstract: A conferencing assembly for use with at least one computer, the assembly including a table top forming a table top opening, a leg support structure, a display screen supported adjacent the top surface, a switcher for controlling input to the display screen, a plurality of handsets, each hand set including a selector button usable to send a signal to the switcher thereby causing the switcher to link a computer associated with the selector button to the display, a plurality of handset cables, each handset cable having first and second ends linked to the switcher and an associated selector button, respectively, for passing signals from the selector buttons to the switcher, a take up assembly including a separate weight for each of the handset cables, the take up assembly disposed below the top member and aligned with the top opening, each handset cable linked to an associated weight, each weight applying a force tending to pull the second end of the associated handset cable into the opening.

Abstract: A multiple supply voltage device includes an input/output (I/O) network operative at a first supply voltage, a core network coupled to the I/O network and operative at a second supply voltage, and a power-on-control (POC) network coupled to the I/O network and the core network. The POC network is configured to transmit a POC signal to the I/O network and includes an adjustable current power up/down detector configured to detect a power state of the core network. The POC network also includes processing circuitry coupled to the adjustable current power up/down detector and configured to process the power state into the POC signal, and one or more feedback circuits. For reducing the leakage current while also improving the power-up/down detection speed, the feedback circuit(s) are coupled to the adjustable current power up/down detector and configured to provide feedback signals to adjust a current capacity of the adjustable current power up/down detector.

Abstract: A protection system implemented on one die of a multi-die package provides a discharge path for excess voltages incurred on one or more other die of the package. Ground paths are provided for certain circuitry in the package that have high noise-sensitivity, and ground paths are provided for certain circuitry in the package that have low noise-sensitivity relative to the high noise-sensitivity circuitry. The grounds of high noise-sensitivity circuitry of multiple die are shorted together, resulting in a common high noise-sensitivity ground. The grounds of low noise-sensitivity circuitry of multiple die are shorted together, resulting in a common low noise-sensitivity ground. A pre-designated removable path is included on the package external to the die, which shorts the common high noise-sensitivity ground and the common low noise-sensitivity ground. The removable path may be removed during manufacturing, if noise present on the shorted grounds results in unacceptable performance degradation.