Patents by Inventor Vivek Tripathi
Vivek Tripathi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11451240Abstract: A quad signal generator circuit generates four 2N-1 bit control signals in response to a 2N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2N-1 bit control signals. Outputs of the 2N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2N-1 bit thermometer coded signal and a time delay applied to the 2N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N-1 bit thermometer coded signal.Type: GrantFiled: June 10, 2021Date of Patent: September 20, 2022Assignee: STMicroelectronics International N.V.Inventor: Vivek Tripathi
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Patent number: 11417371Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.Type: GrantFiled: July 13, 2021Date of Patent: August 16, 2022Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Rupesh Singh, Vivek Tripathi
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Publication number: 20220029636Abstract: A quad signal generator circuit generates four 2N-1 bit control signals in response to a 2N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2N-1 bit control signals. Outputs of the 2N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2N-1 bit thermometer coded signal and a time delay applied to the 2N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N-1 bit thermometer coded signal.Type: ApplicationFiled: June 10, 2021Publication date: January 27, 2022Applicant: STMicroelectronics International N.V.Inventor: Vivek TRIPATHI
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Patent number: 11200267Abstract: A system for automated classifying of electronic messages is disclosed. The system may receive an electronic message comprising a text including a message body and a metadata. The system may determine a case status based on the metadata and extract a set of events form the message body in response to the case status. The system may determine a case type based on the set of events and a set of case types. The system may generate a new case event in a case management system based on the case type.Type: GrantFiled: June 26, 2019Date of Patent: December 14, 2021Assignee: American Express Travel Related Services CompanyInventors: Chetana Kadatoka, Edward K. Samson, Vivek Tripathi
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Publication number: 20210343319Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.Type: ApplicationFiled: July 13, 2021Publication date: November 4, 2021Applicant: STMicroelectronics International N.V.Inventors: Ankur BAL, Rupesh SINGH, Vivek TRIPATHI
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Patent number: 11152951Abstract: A quad signal generator circuit generates four 2N?1 bit control signals in response to a sampling clock and a 2N?1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N?1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2N?1 bit control signals. Outputs of the 2N?1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2N?1 bit control signals such that all logic states of bits of the four 2N?1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N?1 bit thermometer coded signal.Type: GrantFiled: November 16, 2020Date of Patent: October 19, 2021Assignee: STMicroelectronics International N.V.Inventor: Vivek Tripathi
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Patent number: 11094354Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.Type: GrantFiled: September 9, 2020Date of Patent: August 17, 2021Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Rupesh Singh, Vivek Tripathi
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Publication number: 20210184691Abstract: A quad signal generator circuit generates four 2N?1 bit control signals in response to a sampling clock and a 2N?1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N?1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2N?1 bit control signals. Outputs of the 2N?1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2N?1 bit control signals such that all logic states of bits of the four 2N?1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N?1 bit thermometer coded signal.Type: ApplicationFiled: November 16, 2020Publication date: June 17, 2021Applicant: STMicroelectronics International N.V.Inventor: Vivek TRIPATHI
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Publication number: 20210110852Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.Type: ApplicationFiled: September 9, 2020Publication date: April 15, 2021Applicant: STMicroelectronics International N.V.Inventors: Ankur BAL, Rupesh SINGH, Vivek TRIPATHI
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Publication number: 20200409981Abstract: A system for automated classifying of electronic messages is disclosed. The system may receive an electronic message comprising a text including a message body and a metadata. The system may determine a case status based on the metadata and extract a set of events form the message body in response to the case status. The system may determine a case type based on the set of events and a set of case types. The system may generate a new case event in a case management system based on the case type.Type: ApplicationFiled: June 26, 2019Publication date: December 31, 2020Applicant: AMERICAN EXPRESS TRAVEL RELATED SERVICES COMPANY, INC.Inventors: CHETANA KADATOKA, EDWARD K. SAMSON, VIVEK TRIPATHI
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Patent number: 10148277Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.Type: GrantFiled: May 19, 2017Date of Patent: December 4, 2018Assignee: STMicroelectronics International N.V.Inventors: Pratap Narayan Singh, Vivek Tripathi, Anil Kumar, Rakesh Malik
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Publication number: 20180337685Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.Type: ApplicationFiled: May 19, 2017Publication date: November 22, 2018Applicant: STMicroelectronics International N.V.Inventors: Pratap Narayan Singh, Vivek Tripathi, Anil Kumar, Rakesh Malik
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Publication number: 20170153791Abstract: This disclosure relates to systems and methods for modifying icon pixels using a badge algorithm. In one example, a method includes receiving an indicator that media content is available, the indicator identifying a badge algorithm among a plurality of badge algorithms; rendering icon pixels to a graphics memory; executing the badge algorithm to modify one or more of the icon pixels by writing to the graphics memory; and causing the icon pixels to be displayed on a display screen.Type: ApplicationFiled: December 17, 2015Publication date: June 1, 2017Inventors: Samish Chandra Kolli, Tomer Cohen, Vivek Tripathi, Aarthi Jayaram, Corine Yang