Abstract: An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.

Abstract: An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.

Abstract: An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.

Abstract: A video processing device includes a video preprocessor and a video processor. The video processor is configured to facilitate inputting preprocessed digital video data ready for further processing by an encoder or a transcoder, compressing the preprocessed digital video data to form compressed digital video data, and outputting the compressed digital video data. The video preprocessor operable to receive digital video raw data, configured to facilitate preprocessing a macroblock of the digital video raw data so as to output the preprocessed digital video data ready for an encoder or transcoder of the video processor when the macroblock does not indicate SKIP, and not preprocessing the macroblock of the digital video raw data when the macroblock is a SKIP macroblock indicating SKIP, but jumping to process the SKIP macroblock by an entropy encoder of the video processor instead.

Abstract: An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.

Abstract: An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.

Abstract: A network media gateway is disclosed with a processor configured to include a plurality of decoder channels, a plurality of overlay channels, an overlay renderer, a video mixer, and an encoder channel. A digital signal processor embedded in a network media gateway is also disclosed, and a mixing method implemented on a digital signal processor is also disclosed.

Abstract: A video processing device is disclosed that includes a processor unit with a processor and a memory having a reorder buffer. The processor includes a reorder module, a frame rate conversion module, and post-processing function modules. The reorder, frame rate conversion, and post-processing modules access video frames stored in the reorder buffer, while the video frames are stored in the reorder buffer, and reorder, adjust the frame rate, and perform image processing, respectively, on the video frames, while the video frames are stored in the reorder buffer. A method implemented on such a video processing device is also disclosed. A computer-readable storage medium with instructions stored thereon for performing the method is also disclosed.

Abstract: An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.

Abstract: A network media gateway is disclosed with a processor configured to include a plurality of decoder channels, a plurality of overlay channels, an overlay renderer, a video mixer, and an encoder channel. A digital signal processor embedded in a network media gateway is also disclosed, and a mixing method implemented on a digital signal processor is also disclosed.

Abstract: A video processing device includes a video preprocessor and a video processor. The video processor is configured to facilitate inputting preprocessed digital video data ready for further processing by an encoder or a transcoder, compressing the preprocessed digital video data to form compressed digital video data, and outputting the compressed digital video data. The video preprocessor operable to receive digital video raw data, configured to facilitate preprocessing a macroblock of the digital video raw data so as to output the preprocessed digital video data ready for an encoder or transcoder of the video processor when the macroblock does not indicate SKIP, and not preprocessing the macroblock of the digital video raw data when the macroblock is a SKIP macroblock indicating SKIP, but jumping to process the SKIP macroblock by an entropy encoder of the video processor instead.