Patents by Inventor Vladimir M. Parkun

Vladimir M. Parkun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making multilevel interconnections of electronic parts
    Patent number: 5880021
    Abstract: A process for forming a multilevel electronic interconnect structure, the electronic interconnect structure having level conductive paths parallel to a substrate and interlevel electrical interconnections perpendicular to the substrate, the process comprising providing a main aluminum layer over the substrate surface, defining level conductive paths by forming a blocking mask on the main aluminum layer, the blocking mask leaving exposed areas corresponding to the level conductive paths, carrying out a barrier anodization process on the main aluminum layer to form a surface barrier oxide over the level conductive paths, removing the blocking mask, providing an upper aluminum layer over the main aluminum layer, defining interlevel interconnections by forming a blocking mask on the upper aluminum layer, the blocking mask covering areas corresponding to the interlevel interconnections, and subjecting the main and upper aluminum layers to porous anodization.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: March 9, 1999
    Assignee: East/West Technology Partners, Ltd.
    Inventors: Vladimir A. Labunov, Vitaly A. Sokol, Vladimir M. Parkun, Alla I. Vorob'yova
  • Process for making multilevel interconnections of electronic components
    Patent number: 5580825
    Abstract: A process for forming a multilevel electronic interconnect structure, the electronic interconnect structure having level conductive paths parallel to a substrate and interlevel electrical interconnections perpendicular to the substrate, the process comprising providing a main aluminum layer over the substrate surface, defining level conductive paths by forming a blocking mask on the main aluminum layer, the blocking mask leaving exposed areas corresponding to the level conductive paths, carrying out a barrier anodization process on the main aluminum layer to form a surface barrier oxide over the level conductive paths, removing the blocking mask, providing an upper aluminum layer over the main aluminum layer, defining interlevel interconnections by forming a blocking mask on the upper aluminum layer, the blocking mask covering areas corresponding to the interlevel interconnections, and subjecting the main and upper aluminum layers to porous anodization.
    Type: Grant
    Filed: September 20, 1993
    Date of Patent: December 3, 1996
    Assignee: International Technology Exchange Corp.
    Inventors: Vladimir A. Labunov, Vitaly A. Sokol, Vladimir M. Parkun, Alla I. Vorob'yova