Patents by Inventor Vladimir Machkaoutsan
Vladimir Machkaoutsan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11690210Abstract: Disclosed are monolithically integrated three-dimensional (3D) DRAM array structures that include one-transistor, one-capacitor (1T1C) cells embedded at multiple device tiers of a layered substrate assembly. In some embodiments, vertical electrically conductive data-line and ground pillars extending through the substrate assembly provide the transistor source and ground voltages, and horizontal electrically conductive access lines at multiple device levels provide the transistor gate voltages. Process flows for fabricating the 3D DRAM arrays are also described.Type: GrantFiled: December 27, 2019Date of Patent: June 27, 2023Assignee: Micron Technology, Inc.Inventors: Vladimir Machkaoutsan, Richard J. Hill
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Patent number: 11549177Abstract: Methods are disclosed herein for depositing a passivation layer comprising fluorine over a dielectric material that is sensitive to chlorine, bromine, and iodine. The passivation layer can protect the sensitive dielectric layer thereby enabling deposition using precursors comprising chlorine, bromine, and iodine over the passivation layer.Type: GrantFiled: December 10, 2019Date of Patent: January 10, 2023Assignee: ASM INTERNATIONAL, N.V.Inventors: Tom E. Blomberg, Eva E. Tois, Robert Huggare, Jan Willem Maes, Vladimir Machkaoutsan, Dieter Pierreux
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Publication number: 20210343640Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.Type: ApplicationFiled: July 13, 2021Publication date: November 4, 2021Applicant: Micron Technology, Inc.Inventors: Vladimir Machkaoutsan, Pieter Blomme, Emilio Camerlenghi, Justin B. Dorhout, Jian Li, Ryan L. Meyer, Paolo Tessariol
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Patent number: 11094627Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.Type: GrantFiled: October 25, 2019Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventors: Vladimir Machkaoutsan, Pieter Blomme, Emilio Camerlenghi, Justin B. Dorhout, Jian Li, Ryan L. Meyer, Paolo Tessariol
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Patent number: 11088070Abstract: A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.Type: GrantFiled: July 22, 2020Date of Patent: August 10, 2021Assignee: IMEC vzwInventors: Basoene Briggs, Vladimir Machkaoutsan, Zsolt Tokei
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Publication number: 20210125919Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.Type: ApplicationFiled: October 25, 2019Publication date: April 29, 2021Applicant: Micron Technology, Inc.Inventors: Vladimir Machkaoutsan, Pieter Blomme, Emilio Camerlenghi, Justin B. Dorhout, Jian Li, Ryan L. Meyer, Paolo Tessariol
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Publication number: 20210028106Abstract: A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.Type: ApplicationFiled: July 22, 2020Publication date: January 28, 2021Inventors: Basoene Briggs, Vladimir Machkaoutsan, Zsolt Tokei
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Publication number: 20200212041Abstract: Disclosed are monolithically integrated three-dimensional (3D) DRAM array structures that include one-transistor, one-capacitor (1T1C) cells embedded at multiple device tiers of a layered substrate assembly. In some embodiments, vertical electrically conductive data-line and ground pillars extending through the substrate assembly provide the transistor source and ground voltages, and horizontal electrically conductive access lines at multiple device levels provide the transistor gate voltages. Process flows for fabricating the 3D DRAM arrays are also described.Type: ApplicationFiled: December 27, 2019Publication date: July 2, 2020Inventors: Vladimir Machkaoutsan, Richard J. Hill
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Publication number: 20200181769Abstract: Methods are disclosed herein for depositing a passivation layer comprising fluorine over a dielectric material that is sensitive to chlorine, bromine, and iodine. The passivation layer can protect the sensitive dielectric layer thereby enabling deposition using precursors comprising chlorine, bromine, and iodine over the passivation layer.Type: ApplicationFiled: December 10, 2019Publication date: June 11, 2020Inventors: Tom E. Blomberg, Eva E. Tois, Robert Huggare, Jan Willem Maes, Vladimir Machkaoutsan, Dieter Pierreux
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Publication number: 20200083116Abstract: A method of forming gate contacts and/or contact lines on a plurality of fins. The method comprises providing a wafer comprising a semiconductor structure which comprises a plurality of fins. The method further comprises patterning at least one continuous trench over the fins, and filling at least one of the trenches with metal to obtain at least one continuous gate in contact with the fins and/or filling at least one of the trenches with metal to obtain at least one continuous contact line in contact with the fins. The method further comprises cutting the metal of the at least one gate and/or cutting the metal of the at least one contact line in between some of the fins.Type: ApplicationFiled: September 11, 2019Publication date: March 12, 2020Inventors: Steven Demuynck, Geert Eneman, Vladimir Machkaoutsan
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Patent number: 10513772Abstract: Methods are disclosed herein for depositing a passivation layer comprising fluorine over a dielectric material that is sensitive to chlorine, bromine, and iodine. The passivation layer can protect the sensitive dielectric layer thereby enabling deposition using precursors comprising chlorine, bromine, and iodine over the passivation layer.Type: GrantFiled: October 14, 2010Date of Patent: December 24, 2019Assignee: ASM International N.V.Inventors: Tom E. Blomberg, Eva E. Tois, Robert Huggare, Jan Willem Maes, Vladimir Machkaoutsan, Dieter Pierreux
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Patent number: 10361201Abstract: Semiconductor structures, devices, and methods of forming the structures and device are disclosed. Exemplary structures include multi-gate or FinFET structures that can include both n-channel MOS (NMOS) and p-channel MOS (PMOS) devices to form CMOS structures and devices on a substrate. The devices can be formed using selective epitaxy and shallow trench isolation techniques.Type: GrantFiled: January 18, 2016Date of Patent: July 23, 2019Assignee: ASM IP Holding B.V.Inventors: Qi Xie, Vladimir Machkaoutsan, Jan Willem Maes
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Publication number: 20190067435Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.Type: ApplicationFiled: October 25, 2018Publication date: February 28, 2019Inventors: Mustafa Badaroglu, Vladimir Machkaoutsan, Stanley Seungchul Song, Jeffrey Junhao Xu, Matthew Michael Nowak, Choh Fei Yeap
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Patent number: 10186459Abstract: The present disclosure relates to methods and structures that involve the use of directed self-assembly to selectively remove at least one fin or fin section from a pattern of parallel fins in a semiconductor structure.Type: GrantFiled: September 14, 2017Date of Patent: January 22, 2019Assignee: IMEC VZWInventors: Roel Gronheid, Vladimir Machkaoutsan
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Patent number: 10157992Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.Type: GrantFiled: December 28, 2015Date of Patent: December 18, 2018Assignee: QUALCOMM IncorporatedInventors: Mustafa Badaroglu, Vladimir Machkaoutsan, Stanley Seungchul Song, Jeffrey Junhao Xu, Matthew Michael Nowak, Choh Fei Yeap
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Patent number: 10079293Abstract: A method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.Type: GrantFiled: December 12, 2017Date of Patent: September 18, 2018Assignee: QUALCOMM IncorporatedInventors: Jeffrey Junhao Xu, Kern Rim, John Jianhong Zhu, Stanley Seungchul Song, Mustafa Badaroglu, Vladimir Machkaoutsan, Da Yang, Choh Fei Yeap
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Patent number: 10043796Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.Type: GrantFiled: April 12, 2016Date of Patent: August 7, 2018Assignee: QUALCOMM IncorporatedInventors: Vladimir Machkaoutsan, Stanley Seungchul Song, Mustafa Badaroglu, John Jianhong Zhu, Junjing Bao, Jeffrey Junhao Xu, Da Yang, Matthew Michael Nowak, Choh Fei Yeap
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Patent number: 10032678Abstract: Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an exemplary CMOS device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires. Vertically adjacent nanowires are connected at narrow top and bottom end portions of each nanowire. Thus, the nanowire channel structure comprises a plurality of narrow portions that are narrower than a corresponding plurality of central portions. A wrap-around gate material is disposed around the nanowire channel structure, including the plurality of narrow portions, without entirely wrapping around any nanowire therein. The exemplary CMOS device provides, for example, a larger effective channel width and better gate control than a conventional fin field-effect transistor (FET) (FinFET) of a similar footprint. The exemplary CMOS device further provides, for example, a shorter nanowire channel structure than a conventional nanowire FET.Type: GrantFiled: June 30, 2016Date of Patent: July 24, 2018Assignee: QUALCOMM IncorporatedInventors: Jeffrey Junhao Xu, Stanley Seungchul Song, Da Yang, Vladimir Machkaoutsan, Mustafa Badaroglu, Choh Fei Yeap
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Publication number: 20180114848Abstract: A method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.Type: ApplicationFiled: December 12, 2017Publication date: April 26, 2018Inventors: Jeffrey Junhao Xu, Kern Rim, John Jianhong Zhu, Stanley Seungchul Song, Mustafa Badaroglu, Vladimir Machkaoutsan, Da Yang, Choh Fei Yeap
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Patent number: 9953979Abstract: A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all surface area of a regrown source/drain region of the semiconductor device proximate to the gate stack.Type: GrantFiled: March 30, 2015Date of Patent: April 24, 2018Assignee: QUALCOMM IncorporatedInventors: Jeffrey Junhao Xu, Stanley Seungchul Song, Vladimir Machkaoutsan, Mustafa Badaroglu, Junjing Bao, John Jianhong Zhu, Da Yang, Choh Fei Yeap