Patents by Inventor Vladimir Zlatkovic
Vladimir Zlatkovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230111161Abstract: An apparatus for processing an input signal from a memory includes an attenuator circuit and an analog front end (AFE) circuit. The attenuator circuit attenuates the input signal from the memory to produce an attenuated signal. The AFE circuit includes a first amplification stage and a second amplification stage. The first amplification stage has an n-type metal-oxide semiconductor (NMOS) transistor. The NMOS transistor has a gate that receives the attenuated signal from the attenuator circuit. The second amplification stage has a p-type metal-oxide semiconductor (PMOS) transistor. The PMOS transistor has a gate that receives the attenuated signal from the attenuator circuit. Outputs of the first amplification stage and the second amplification stage are electrically coupled to a common output of the AFE circuit.Type: ApplicationFiled: October 4, 2022Publication date: April 13, 2023Inventors: Xiao YUN, Vladimir ZLATKOVIC
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Patent number: 11569806Abstract: Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry.Type: GrantFiled: February 2, 2022Date of Patent: January 31, 2023Assignee: Synopsys, Inc.Inventors: Kuan Zhou, David Da-Wei Lin, Vladimir Zlatkovic, Shefali Walia, Youssef Mamdouh El-Toukhy, Abdelrahman Alaa Gouda, Alexander A. Alexeyev
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Publication number: 20220247398Abstract: Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry.Type: ApplicationFiled: February 2, 2022Publication date: August 4, 2022Inventors: Kuan ZHOU, David Da-Wei LIN, Vladimir ZLATKOVIC, Shefali WALIA, Youssef Mamdouh EL-TOUKHY, Abdelrahman Alaa GOUDA, Alexander A. ALEXEYEV
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Patent number: 9698759Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.Type: GrantFiled: May 5, 2014Date of Patent: July 4, 2017Assignee: ANALOG DEVICES, INC.Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
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Patent number: 9312831Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.Type: GrantFiled: October 1, 2013Date of Patent: April 12, 2016Assignee: ANALOG DEVICES, INC.Inventors: Eric Nestler, Vladimir Zlatkovic, Jeffrey Venuti
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Publication number: 20150381146Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.Type: ApplicationFiled: May 5, 2014Publication date: December 31, 2015Applicant: Analog Devices, Inc.Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
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Patent number: 9218318Abstract: Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.Type: GrantFiled: May 29, 2012Date of Patent: December 22, 2015Assignee: Analog Devices, Inc.Inventors: Eric Nestler, Vladimir Zlatkovic
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Patent number: 9036420Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: GrantFiled: May 15, 2012Date of Patent: May 19, 2015Assignee: ANALOG DEVICES, INC.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Jeffrey Venuti, Alexander Alexeyev, Eric Nestler, David Reynolds, William Bradley, Vladimir Zlatkovic
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Publication number: 20140233773Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.Type: ApplicationFiled: October 1, 2013Publication date: August 21, 2014Applicant: Analog Devices, Inc.Inventors: Eric Nestler, Vladimir Zlatkovic, Jeffrey Venuti
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Patent number: 8717094Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.Type: GrantFiled: June 6, 2012Date of Patent: May 6, 2014Assignee: Analog Devices, Inc.Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
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Patent number: 8547272Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.Type: GrantFiled: August 18, 2011Date of Patent: October 1, 2013Assignee: Analog Devices, Inc.Inventors: Eric Nestler, Vladimir Zlatkovic, Jeffrey Venuti
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Publication number: 20130207827Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.Type: ApplicationFiled: August 18, 2011Publication date: August 15, 2013Applicant: Analog Devices, Inc.Inventors: Eric Nestler, Vladimir Zlatkovic, Jeffrey Venuti
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Publication number: 20130080497Abstract: Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.Type: ApplicationFiled: May 29, 2012Publication date: March 28, 2013Applicant: Analog Devices, Inc.Inventors: Eric Nestler, Vladimir Zlatkovic
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Publication number: 20120306569Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.Type: ApplicationFiled: June 6, 2012Publication date: December 6, 2012Applicant: Analog Devices, Inc.Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
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Patent number: 8188753Abstract: Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.Type: GrantFiled: August 21, 2009Date of Patent: May 29, 2012Assignee: Analog Devices, Inc.Inventors: Eric Nestler, Vladimir Zlatkovic
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Patent number: 8179731Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: GrantFiled: August 6, 2009Date of Patent: May 15, 2012Assignee: Analog Devices, Inc.Inventors: Benjamin Vigoda, Eric Nestler, Jeffrey Bernstein, David Reynolds, Alexander Alexeyev, Jeffrey Venuti, William Bradley, Vladimir Zlatkovic
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Patent number: 8107306Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: GrantFiled: August 6, 2009Date of Patent: January 31, 2012Assignee: Analog Devices, Inc.Inventors: Benjamin Vigoda, Eric Nestler, Jeffrey Bernstein, David Reynolds, Alexander Alexeyev, Jeffrey Venuti, William Bradley, Vladimir Zlatkovic
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Publication number: 20100207644Abstract: Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.Type: ApplicationFiled: August 21, 2009Publication date: August 19, 2010Applicant: Lyric Semiconductor, Inc.Inventors: Eric Nestler, Vladimir Zlatkovic
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Patent number: 7402985Abstract: A voltage regulator comprising two feedback loops for regulating a load voltage, where the first feedback loop comprises a pass transistor to source current to the load, and the second feedback loop comprises a shunt transistor to shunt current from the pass transistor to ground. The use of two feedback loops allows the design of a voltage regulator in which it small-signal impedance, as seen by a power rail, has a phase not less than ?90 degrees. This mitigates interactions between the power rail and the voltage regulator that may lead to oscillations, without the need for a relatively large de-coupling capacitor. Other embodiments are described and claimed.Type: GrantFiled: September 6, 2006Date of Patent: July 22, 2008Assignee: Intel CorporationInventor: Vladimir Zlatkovic
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Publication number: 20080054861Abstract: A voltage regulator comprising two feedback loops for regulating a load voltage, where the first feedback loop comprises a pass transistor to source current to the load, and the second feedback loop comprises a shunt transistor to shunt current from the pass transistor to ground. The use of two feedback loops allows the design of a voltage regulator in which it small-signal impedance, as seen by a power rail, has a phase not less than ?90 degrees. This mitigates interactions between the power rail and the voltage regulator that may lead to oscillations, without the need for a relatively large de-coupling capacitor. Other embodiments are described and claimed.Type: ApplicationFiled: September 6, 2006Publication date: March 6, 2008Inventor: Vladimir Zlatkovic