Abstract: A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.

Abstract: A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.

Abstract: A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.

Abstract: A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.

Abstract: A back-end metallization structure for non-volatile memory (NVM) and other semiconductor devices including low-moisture-content oxide cap layers that suppress the creation and migration of mobile hydrogen atoms/ions during back-end processing. The metallization structure includes multiple metallization layers formed over front-end e.g., polysilicon (floating gate) structures and a pre-metal dielectric layer. Each metallization layer includes a patterned metal (e.g., aluminum) structure covered by an interlevel dielectric (ILD) layer (e.g., BPSG, USG or FSG). Each cap layer is formed using a high-density low-moisture content oxide such as silane oxide (i.e.

Abstract: A back-end metallization structure for non-volatile memory (NVM) and other semiconductor devices including low-moisture-content oxide cap layers that suppress the creation and migration of mobile hydrogen atoms/ions during back-end processing. The metallization structure includes multiple metallization layers formed over front-end e.g., polysilicon (floating gate) structures and a pre-metal dielectric layer. Each metallization layer includes a patterned metal (e.g., aluminum) structure covered by an interlevel dielectric (ILD) layer (e.g., BPSG, USG or FSG). Each cap layer is formed using a high-density low-moisture content oxide such as silane oxide (i.e.

Abstract: A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).

Abstract: Solid state radiation sensors include a floating gate (FG) structure having a large control capacitor region disposed on thick dielectric portion over a control gate (CG) implemented by an isolated P-well region, and a tunneling capacitor region disposed on thin gate oxide dielectric over another tunneling gate (TG) isolated P-well region. Opposite voltages (e.g., +5V/?5V) are respectively applied to the CG and TG P-well regions to charge the FG structure by Fowler-Nordheim tunneling. During exposure, radiation striking the sensor discharges the FG structure by generating electron-hole pairs in the dielectric portion separating the CG P-well region and the control capacitor region. After exposure, the total ionizing dose (TID) is calculated, e.g., by measuring the threshold voltage shift of a CMOS readout inverter controlled by the residual charge stored on the FG structure. Sensor performance is enhanced by metal plates, utilizing two control capacitors, or modifying the FG electrode layout.

Abstract: A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).

Abstract: A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The output circuit includes PMOS and NMOS select transistors. The PMOS inverter and select transistors share a common source/drain region. Similarly, the NMOS inverter and select transistors share a common source/drain region. This configuration minimizes the required layout area of the non-volatile memory cell and allows design of arrays with smaller footprints. Alternately, the tunneling capacitor may be excluded, further reducing the required layout area of the NVM cell.

Abstract: A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The output circuit includes PMOS and NMOS select transistors. The PMOS inverter and select transistors share a common source/drain region. Similarly, the NMOS inverter and select transistors share a common source/drain region. This configuration minimizes the required layout area of the non-volatile memory cell and allows design of arrays with smaller footprints. Alternately, the tunneling capacitor may be excluded, further reducing the required layout area of the NVM cell.