Patents by Inventor Vladislav Vassiliev

Vladislav Vassiliev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6500771
    Abstract: A method for fabricating a boron-contained silicate glass layers, such as borosilicate and borophosphosilicate glass films at low temperature using High Density Plasma CVD with silane derivatives as a source of silicon, boron and phosphorus compounds as a doping compounds, oxygen is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in reactor chamber. Key feature of the invention's process is a flow capability of boron-contained silicate glass materials which provide a film with good film integrity and void-free gap-fill within the steps of device structures after low temperature thermal budget anneal conditions.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: December 31, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Vladislav Vassiliev, John Leonard Sudijono, Alan Cuthbertson
  • Patent number: 6355581
    Abstract: A method for fabricating a silicon oxide and silicon glass layers at low temperature using High Density Plasma CVD with silane or inorganic or organic silane derivatives as a source of silicon, inorganic compounds containing boron, phosphorus, and fluorine as a doping compounds, oxygen, and gas additives is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in reactor chamber. Key feature of the invention's process is a silicon source to gas additive mole ratio, which is maintained depending on the used compound and deposition process conditions. Inorganic halide-containing compounds are used as gas additives. This feature provides the reaction conditions for the proper reaction performance that allows a deposition of a film with. good film integrity and void-free gap-fill within the steps of device structures.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: March 12, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Vladislav Vassiliev, John Leonard Sudijono, Yelehanka Ramachandramurthy Pradeep, Jie Yu
  • Patent number: 6197705
    Abstract: A method for fabricating a silicon oxide and silicon glass layers at low temperature using soft power-optimized Plasma-Activated CVD with a TEOS-ozone-oxygen reaction gas mixture (TEOS O3/O2 PACVD) is described. It combines advantages of both low temperature Plasma-Enhanced Chemical Vapor Deposition (PECVD) and TEOS-ozone Sub-Atmospheric Chemical Vapor Deposition (SACVD) and yields a coating of silicon oxide with stable and high deposition rate, no surface sensitivity, good film properties, conformal step coverage and good gap-fill. Key features of the invention's O3/O2 PACVD process are: a plasma is maintain throughout the entire deposition step in a parallel plate type reactor chamber, the precise RF plasma density, ozone concentration in oxygen and the deposition temperature. These features provide the reaction conditions for the proper O3/O2 reaction mechanism that deposits a conformal silicon oxide layer.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: March 6, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Vladislav Vassiliev
  • Patent number: 6180490
    Abstract: This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to an improved method of filling shallow trenches, in shallow trench isolation, STI sub-quarter micron technology. The present method relates to a process for forming trench gap filling with chemically vapor deposited (CVD) silicon dioxide layers within trenches within substrates employed in integrated circuit fabrication. There is first provided a silicon substrate having a trench formed therein. There is then formed a silicon dioxide layer through tetraethylorthosilicate (TEOS) and ozone reaction, at either sub-atmospheric, or atmospheric pressure, with enhanced surface sensitivity features, which lines the trench providing corner rounding. Then there is a thermal oxidation to form within the trench a thermal silicon dioxide layer underneath the TEOS-ozone trench silicon dioxide liner.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: January 30, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Vladislav Vassiliev, Igor Peidous