Patents by Inventor Volker Hecht
Volker Hecht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11031078Abstract: A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.Type: GrantFiled: March 25, 2019Date of Patent: June 8, 2021Assignee: Microsemi SoC Corp.Inventors: Fengliang Xue, Fethi Dhaoui, Pavan Singaraju, Victor Nguyen, John L. McCollum, Volker Hecht
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Publication number: 20200286559Abstract: A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.Type: ApplicationFiled: March 25, 2019Publication date: September 10, 2020Applicant: Microsemi SoC Corp.Inventors: Fengliang Xue, Fethi Dhaoui, Pavan Singaraju, Victor Nguyen, John L. McCollum, Volker Hecht
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Patent number: 10523208Abstract: A 4-input lookup table module including eight first-rank 2-input multiplexers, four second-rank multiplexers, two third-rank multiplexers, and one fourth-rank multiplexer, the first-rank through fourth-rank multiplexers forming a tree structure. A select input of the fourth-rank multiplexer is coupled to a first input node. Select inputs of the third-rank multiplexers are coupled to a second input node. Select inputs of a first and a second adjacent ones of the second rank 2-input multiplexers are electrically isolated from select inputs of a third and a fourth adjacent ones of the second rank 2-input multiplexers. Select inputs of a first through a fourth adjacent ones of the first rank 2-input multiplexers are electrically isolated from select inputs of a fifth through an eighth adjacent ones of the first rank 2-input multiplexers.Type: GrantFiled: October 31, 2018Date of Patent: December 31, 2019Assignee: Microsemi SoC Corp.Inventors: Volker Hecht, Jonathan W. Greene
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Publication number: 20190228825Abstract: A static random-access memory (SRAM) cell includes a non-inverting logic element having an input and an output. A vertical resistor feedback device is connected between the output and the input of the non-inverting logic element.Type: ApplicationFiled: January 15, 2019Publication date: July 25, 2019Applicant: Microsemi SoC Corp.Inventors: Volker Hecht, John L. McCollum
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Publication number: 20190229734Abstract: A buffered multiplexer includes a multiplexer having N multiplexer inputs each input selectively coupleable to a single multiplexer output. A non-inverting buffer has an input coupled to the multiplexer output and an output forming the output node of the buffered multiplexer. At least one vertical resistor is coupled between the input and the output of the non-inverting buffer.Type: ApplicationFiled: January 16, 2019Publication date: July 25, 2019Applicant: Microsemi SoC Corp.Inventors: Volker Hecht, John L. McCollum
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Publication number: 20190165788Abstract: A 4-input lookup table module including eight first-rank 2-input multiplexers, four second-rank multiplexers, two third-rank multiplexers, and one fourth-rank multiplexer, the first-rank through fourth-rank multiplexers forming a tree structure. A select input of the fourth-rank multiplexer is coupled to a first input node. Select inputs of the third-rank multiplexers are coupled to a second input node. Select inputs of a first and a second adjacent ones of the second rank 2-input multiplexers are electrically isolated from select inputs of a third and a fourth adjacent ones of the second rank 2-input multiplexers. Select inputs of a first through a fourth adjacent ones of the first rank 2-input multiplexers are electrically isolated from select inputs of a fifth through an eighth adjacent ones of the first rank 2-input multiplexers.Type: ApplicationFiled: October 31, 2018Publication date: May 30, 2019Applicant: Microsemi SoC Corp.Inventors: Volker Hecht, Jonathan W. Greene
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Patent number: 10147485Abstract: A method for preventing over-programming of resistive random access (ReRAM) based memory cells in a ReRAM memory array includes applying a programming voltage in a programming circuit path including a ReRAM memory cell to be programmed, sensing programming current drawn by the ReRAM cell while the programming voltage is applied across the memory cell, and decreasing the programming current as a function of a rise in programming current.Type: GrantFiled: September 25, 2017Date of Patent: December 4, 2018Assignee: Microsemi SoC Corp.Inventor: Volker Hecht
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Patent number: 9990993Abstract: A ReRAM cell array has having at least one row and one column includes first and second complementary bit lines for each row, a word line, a p-word line, and an n-word line for each column. A ReRAM cell at each row and column of the array includes a first ReRAM device, its first end connected to the first complementary bit line of its row, a p-channel transistor, its source connected to a second end of the first ReRAM device, its drain connected to a switch node, its gate connected to the p-channel word line of its column, a second ReRAM device, its first end connected to the second complementary bit line of its row, an n-channel transistor, its source connected to a second end of the second ReRAM device, its drain connected to the switch node, its gate connected to the n-channel word line of its column.Type: GrantFiled: December 9, 2016Date of Patent: June 5, 2018Assignee: Microsemi SoC CorporationInventors: John L. McCollum, Volker Hecht
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Publication number: 20180108409Abstract: A method for preventing over-programming of resistive random access (ReRAM) based memory cells in a ReRAM memory array includes applying a programming voltage in a programming circuit path including a ReRAM memory cell to be programmed, sensing programming current drawn by the ReRAM cell while the programming voltage is applied across the memory cell, and decreasing the programming current as a function of a rise in programming current.Type: ApplicationFiled: September 25, 2017Publication date: April 19, 2018Inventor: Volker Hecht
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Publication number: 20180090205Abstract: A ReRAM cell array has having at least one row and one column includes first and second complementary bit lines for each row, a word line, a p-word line, and an n-word line for each column. A ReRAM cell at each row and column of the array includes a first ReRAM device, its first end connected to the first complementary bit line of its row, a p-channel transistor, its source connected to a second end of the first ReRAM device, its drain connected to a switch node, its gate connected to the p-channel word line of its column, a second ReRAM device, its first end connected to the second complementary bit line of its row, an n-channel transistor, its source connected to a second end of the second ReRAM device, its drain connected to the switch node, its gate connected to the n-channel word line of its column.Type: ApplicationFiled: December 9, 2016Publication date: March 29, 2018Applicant: Microsemi SoC CorporationInventors: John L. McCollum, Volker Hecht
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Patent number: 9704573Abstract: A pair of adjacent ReRAM cells in an array includes a first bit line for a row of the array, a second bit line for the row of the array, a p-channel word line associated with two adjacent columns in the array, and an n-channel word line associated with the two adjacent columns. A pair of ReRAM cells in the adjacent columns in the row each includes a switch node, a first ReRAM device connected between the first bit line and the source of a p-channel transistor. The drain of the p-channel transistor is connected to the switch node, and its gate is connected to the p-channel word line. A second ReRAM device is connected between the second bit line and the source of an n-channel transistor. The drain of the n-channel transistor is connected to the switch node, and its gate is connected to the n-channel word line.Type: GrantFiled: December 9, 2016Date of Patent: July 11, 2017Assignee: Microsemi SoC CorporationInventor: Volker Hecht
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Patent number: 9170774Abstract: A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.Type: GrantFiled: June 12, 2012Date of Patent: October 27, 2015Assignee: Microsemi SoC CorporationInventors: Volker Hecht, Marcel Derevlean, Jonathan Greene
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Patent number: 9103880Abstract: An integrated programmable logic circuit having a read/write probe includes a plurality of programmable logic circuits having internal circuit nodes and a plurality of flip flops, each having an asynchronous data input line, an asynchronous load line, and a data output connected to an internal circuit node, a probe-data line, an address circuit for selecting one of the internal circuit nodes, a read-probe enable line for selectively coupling the selected one of the internal circuit nodes to the probe-data line, a data input path to the asynchronous data input line of each flip flop, a write-probe data input path to the asynchronous data input line of each flip flop, a write-probe enable line, and selection circuitry, responsive to the address circuit and the write-probe enable line, to couple one of the data input path and the write-probe data input path to the asynchronous data input of a selected flip flop.Type: GrantFiled: July 2, 2013Date of Patent: August 11, 2015Assignee: Microsemi SoC CorporationInventors: Jonathan W. Greene, Dirk Kannemacher, Volker Hecht, Theodore Speers
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Patent number: 9000807Abstract: An integrated circuit includes a clock input, a first output, and a second output. A programmable pulse generator has a programmable pulse counter coupled to the clock input at least one control input for receiving count information. A fixed delay element is coupled to the programmable pulse counter. A programmable delay element is coupled to the programmable pulse counter and has at least one control input for receiving delay information. A first multiplexer is coupled to the fixed delay element, the programmable delay element and to the first output. A second multiplexer is coupled to the programmable delay element, the output of the fixed delay element and the second output.Type: GrantFiled: July 2, 2013Date of Patent: April 7, 2015Assignee: Microsemi SoC CorporationInventors: Jonathan W. Greene, Dirk Kannemacher, Volker Hecht, Theodore Speers
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Patent number: 8868820Abstract: A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.Type: GrantFiled: October 31, 2011Date of Patent: October 21, 2014Assignee: Microsemi SoC CorporationInventors: Volker Hecht, Jonathan Greene
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Publication number: 20140006887Abstract: An integrated programmable logic circuit having a read/write probe includes a plurality of programmable logic circuits having internal circuit nodes and a plurality of flip flops, each having an asynchronous data input line, an asynchronous load line, and a data output connected to an internal circuit node, a probe-data line, an address circuit for selecting one of the internal circuit nodes, a read-probe enable line for selectively coupling the selected one of the internal circuit nodes to the probe-data line, a data input path to the asynchronous data input line of each flip flop, a write-probe data input path to the asynchronous data input line of each flip flop, a write-probe enable line, and selection circuitry, responsive to the address circuit and the write-probe enable line, to couple one of the data input path and the write-probe data input path to the asynchronous data input of a selected flip flop.Type: ApplicationFiled: July 2, 2013Publication date: January 2, 2014Inventors: Jonathan W. Greene, Dirk Kannemacher, Volker Hecht, Theodore Speers
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Publication number: 20140002136Abstract: An integrated circuit includes a clock input, a first output, and a second output. A programmable pulse generator has a programmable pulse counter coupled to the clock input at least one control input for receiving count information. A fixed delay element is coupled to the programmable pulse counter. A programmable delay element is coupled to the programmable pulse counter and has at least one control input for receiving delay information. A first multiplexer is coupled to the fixed delay element, the programmable delay element and to the first output. A second multiplexer is coupled to the programmable delay element, the output of the fixed delay element and the second output.Type: ApplicationFiled: July 2, 2013Publication date: January 2, 2014Inventors: Jonathan W. Greene, Dirk Kannemacher, Volker Hecht, Theodore Speers
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Publication number: 20130111119Abstract: A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Inventors: Volker Hecht, Jonathan Greene
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Publication number: 20120259908Abstract: A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.Type: ApplicationFiled: June 12, 2012Publication date: October 11, 2012Inventors: Volker Hecht, Marcel Derevlean, Jonathan Greene
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Patent number: 8255854Abstract: A method for reducing delay in an integrated circuit by compensating for differences in rise and fall delay times comprises creating a timing graph; computing minimum delay tuples for nodes in the timing graph; if there is not at least one feasible delay tuple, determining a longest path and computing minimum delay tuples for the longest path; changing polarities on the longest path to reduce delays; updating the timing graph by transferring new polarity and delay values; performing timing analysis to determine a new longest path if the new longest path is shorter than the prior longest path, accepting a resulting polarity selection and computing minimum delay tuples for the longest path; if the new longest path is not shorter than the prior longest path, accepting a resulting polarity selection and implementing changes in a user-program bitstream.Type: GrantFiled: April 2, 2010Date of Patent: August 28, 2012Assignee: Actel CorporationInventors: Kai Zhu, Volker Hecht