Patents by Inventor Vu Tran

Vu Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240127890
    Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 18, 2024
    Inventors: Hieu Van Tran, THUAN VU, STANLEY HONG, STEPHEN TRINH, ANH LY, NHAN DO, MARK REITEN
  • Patent number: 11960799
    Abstract: Introduced here computer programs and associated computer-implemented techniques for generating measurements of physical structures and environments in an automated matter through analysis of data that is generated by one or more sensors included in a computing device. This can be accomplished by combining insights that are derived through analysis different types of data that are generated, computed, or otherwise obtained by a computing device. For instance, a computer program may enable or facilitate measurement of arbitrary dimensions, angles, and square footage of a physical structure based on (i) images generated by an image sensor included in the corresponding computing device and (ii) measurements generated by an inertial sensor included in the corresponding computing device.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: April 16, 2024
    Assignee: Flyreel, Inc.
    Inventors: Victor Palmer, Vu Tran, Brian Webb, Brian Keller
  • Publication number: 20240119272
    Abstract: In one example, a system comprises an analog neural memory array comprising a plurality of non-volatile memory cells arranged into rows and columns; and a voltage generator to provide a voltage to one or more rows of the analog neural memory array, the voltage generator comprising a voltage ladder to generate a plurality of voltages according to a logarithmic formula.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 11, 2024
    Inventors: HIEU VAN TRAN, THUAN VU, STANLEY HONG, STEPHEN TRINH, STEVEN LEMKE, LOUISA SCHNEIDER, NHAN DO
  • Publication number: 20240112736
    Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to the source line of the array during operation.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 4, 2024
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly, Nhan Do, Mark Reiten
  • Publication number: 20240112003
    Abstract: Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 4, 2024
    Inventors: HIEU VAN TRAN, STEPHEN TRINH, STANLEY HONG, THUAN VU, NGHIA LE, HIEN PHAM
  • Publication number: 20240112729
    Abstract: Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.
    Type: Application
    Filed: December 6, 2022
    Publication date: April 4, 2024
    Inventors: Hieu Van TRAN, Stephen TRINH, Stanley HONG, Thuan VU, Anh LY, Fan LUO
  • Publication number: 20240104357
    Abstract: Numerous examples are disclosed of input circuitry and associated methods in an artificial neural network. In one example, a system comprises a plurality of address decoders to receive an address and output a plurality of row enabling signals in response to the address; a first plurality of registers to store, sequentially, activation data in response to the plurality of row enabling signals; and a second plurality of registers to store, in parallel, activation data received from the first plurality of registers.
    Type: Application
    Filed: December 8, 2022
    Publication date: March 28, 2024
    Inventors: Hieu Van Tran, Stephen Trinh, Stanley Hong, Thuan Vu, Nghia Le, Hien Pham
  • Publication number: 20240104164
    Abstract: Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents, and a plurality of output blocks to receive current from respective columns of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication and generate digital outputs during a read operation of the vector-by-matrix multiplication.
    Type: Application
    Filed: December 13, 2022
    Publication date: March 28, 2024
    Inventors: HIEU VAN TRAN, STEPHEN TRINH, STANLEY HONG, THUAN VU, DUC NGUYEN, HIEN HO PHAM
  • Publication number: 20240105263
    Abstract: In one example, a non-volatile memory system comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to a word line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the word line in response to changes in a voltage of the source line.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Applicant: Silicon Storage Technology, Inc.
    Inventors: Hieu Van TRAN, Thuan VU, Stanley HONG, Stephen TRINH, Anh LY, Nhan DO, Mark REITEN
  • Patent number: 11941129
    Abstract: Embodiments disclosed are directed to a computing system that performs steps to perform enhanced device fingerprinting using user contacts data. The computing system receives, from an application, a first plurality of device attributes identifying a client device on which the application is being used. The first plurality of device attributes includes first device identification data and first user contacts data. Subsequently, when a user is attempting to perform a transaction using the application on the client device, the computing system receives, from the application, a second plurality of device attributes identifying the client device on which the application is being used. The second plurality of device attributes includes second device identification data and second user contacts data. The computing system compares the second plurality of device attributes to the first plurality of device attributes to determine whether the user is authorized to perform the transaction.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: March 26, 2024
    Assignee: Capital One Services, LLC
    Inventors: William Broome, Nicholas Capurso, Timothy Tran, Vu Thuy Ngo
  • Publication number: 20240095509
    Abstract: In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Hieu Van Tran, STANLEY HONG, ANH LY, THUAN VU, HIEN PHAM, KHA NGUYEN, HAN TRAN
  • Publication number: 20240095508
    Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells organized into rows and columns; a plurality of word lines coupled respectively to rows of the vector-by-matrix multiplication array; and a word line driver coupled to the plurality of word lines, the word line driver comprising a plurality of select transistors coupled to a common control line and the plurality of word lines, and a plurality of bias transistors coupled to the plurality of select transistors and capable of providing a bias voltage to a single select transistor in the plurality of select transistors or to all of plurality of select transistors in response to control signals.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: HIEU VAN TRAN, STANLEY HONG, AHN LY, THUAN VU, HIEN PHAM, KHA NGUYEN, HAN TRAN
  • Publication number: 20240098991
    Abstract: In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Toan Le, Nghia Le, Hien Pham
  • Patent number: 11935594
    Abstract: Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: March 19, 2024
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly
  • Patent number: 11928167
    Abstract: In one or more implementations, content generated using a client application may be associated with a classification. A number of classifications may be recommended to users of a client application based on alphanumeric characters entered by the users. Additionally, a number of classifications may be recommended to the users of the client application based one or more additional criteria, such as recently used classifications or classifications having at least a threshold frequency of use by additional users of the client application.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: March 12, 2024
    Assignee: Snap Inc.
    Inventors: Nathan Kenneth Boyd, Andrew Grosvenor Cooper, Suraj Vindana Samaranayake, Vu Tran, Yamill Vallecillo, Yiwen Zhan
  • Publication number: 20240079064
    Abstract: In one example, a system comprises a neural network array of non-volatile memory cells arranged in rows and columns; and a logical cell comprising a first plurality of non-volatile memory cells in a first row of the array and a second plurality of non-volatile memory cells in a second row adjacent to the first row; wherein the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells are configured as one or more coarse cells and one or more fine cells.
    Type: Application
    Filed: April 26, 2023
    Publication date: March 7, 2024
    Inventors: Hieu Van Tran, Stanley Hong, Stephen Trinh, Thuan Vu, Steven Lemke, Vipin Tiwari, Nhan Do
  • Patent number: 11915747
    Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: February 27, 2024
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Vipin Tiwari, Nhan Do
  • Publication number: 20230259667
    Abstract: Introduced here computer programs and associated computer-implemented techniques for generating measurements of physical structures and environments in an automated matter through analysis of data that is generated by one or more sensors included in a computing device. This can be accomplished by combining insights that are derived through analysis different types of data that are generated, computed, or otherwise obtained by a computing device. For instance, a computer program may enable or facilitate measurement of arbitrary dimensions, angles, and square footage of a physical structure based on (i) images generated by an image sensor included in the corresponding computing device and (ii) measurements generated by an inertial sensor included in the corresponding computing device.
    Type: Application
    Filed: April 26, 2023
    Publication date: August 17, 2023
    Inventors: Victor Palmer, Vu Tran, Brian Webb, Brian Keller
  • Publication number: 20230258769
    Abstract: Apparatus and methods are provided for distance calibration of an autonomous vehicle in a nominally short distance calibration environment. In particular, apparatus, methods and systems are provided using reflective materials to artificially augment a distance to a known target. In various implementations, reflective planes are disposed in pathway between the autonomous vehicle and target. Targets of known sizes can be used to calculated a distance from the autonomous vehicle to the target. Utilizing the known optical pathway, a calibration can be performed. With the aid of an Autonomous Vehicle Rotation Table, the autonomous vehicle is rotated such that a matrix of range-angle calibrations can be executed. Frequency spectra include LiDAR and radar, but any suitable bandwidth and/or detection protocol is not beyond the scope of the present disclosure.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Applicant: GM Cruise Holdings LLC
    Inventors: Kenneth Ramon Ferguson, David Xuan Vu Tran, Zachary Matthew Logan Edwards, Philip David Aufdencamp
  • Patent number: 11699001
    Abstract: Introduced here computer programs and associated computer-implemented techniques for generating measurements of physical structures and environments in an automated matter through analysis of data that is generated by one or more sensors included in a computing device. This can be accomplished by combining insights that are derived through analysis different types of data that are generated, computed, or otherwise obtained by a computing device. For instance, a computer program may enable or facilitate measurement of arbitrary dimensions, angles, and square footage of a physical structure based on (i) images generated by an image sensor included in the corresponding computing device and (ii) measurements generated by an inertial sensor included in the corresponding computing device.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: July 11, 2023
    Assignee: Flyreel, Inc.
    Inventors: Victor Palmer, Vu Tran, Brian Webb, Brian Keller