Abstract: A system and method are disclosed for management of sample data to enable video rate anti-aliasing convolution for interlaced video frames. Sample data may be moved simultaneously from a sample buffer to a bin scanline cache and from the bin scanline cache to an array of N2 processor—memory units (e.g., 25 for N=5). Pixel data may be convolved from an N×N sample bin array that may be approximately centered on the pixel location. Since each sample bin contains Ns/b samples, Ns/b×N2 samples may be filtered for each pixel (e.g., 400 for N=5 and Ns/b=16). Each processor—memory unit convolves the sample data for one sample bin in the N×N sample bin array and supports a variety of filter functions. Pixel data may be output to a real time video data stream.

Abstract: A system and method are disclosed for management of sample data to enable video rate anti-aliasing convolution for interlaced video frames. Sample data may be moved simultaneously from a sample buffer to a bin scanline cache and from the bin scanline cache to an array of N2 processor—memory units (e.g. 25 for N=5). Pixel data may be convolved from an N×N sample bin array that may be approximately centered on the pixel location. Since each sample bin contains Ns/b samples, Ns/b×N2 samples may be filtered for each pixel (e.g. 400 for N=5 and Ns/b=16). Each processor—memory unit convolves the sample data for one sample bin in the N×N sample bin array and supports a variety of filter functions. Pixel data may be output to a real time video data stream.

Abstract: A system and method are disclosed for management of sample data to enable video rate anti-aliasing convolution for interlaced video frames. Sample data may be moved simultaneously from a sample buffer to a bin scanline cache and from the bin scanline cache to an array of N2 processor-memory units (e.g., 25 for N=5). Pixel data may be convolved from an N×N sample bin array that may be approximately centered on the pixel location. Since each sample bin contains Ns/b samples, Ns/b×N2 samples may be filtered for each pixel (e.g., 400 for N=5 and Ns/b=16). Each processor-memory unit convolves the sample data for one sample bin in the N×N sample bin array and supports a variety of filter functions. Pixel data may be output to a real time video data stream.

Abstract: A set in structure (SIS) list is established for each DAG structure of a DAG structure network. Additionally, a used before set (UBS) list is established for each structure invoking element in the DAG data structure. At each invocation of a DAG structure, a list of traversal state list (TSL) attribute values that need to saved and subsequently restored (SAR) for the invoking DAG data structure is established. The SAR list of an invoked DAG data structure is established based on a list of attributes needed by the invoking DAG data structure (N) and the SIS of the invoked DAG data structure. The N list is established based on the UBS list of the invoking structure element of the invoking DAG structure, and a need from child (NFC) attribute list of the invoking DAG data structure. Only values of the TSL attributes included in the SAR list are saved before the invoked DAG data structure is traversed.