Abstract: A method, system and computer program for a computer message storage system such as electronic mail. This involves instancing a software archiver to relocate messages according to age and instancing a software backup subsystem to backup storage groups, to maintain a patch file and to copy to a backup file.

Abstract: Embodiments of present invention may provide a method, systems and/or computer program products for initializing a data communications loop. This may involve receiving an information frame relating to a loop initialization primitives, determining how many nodes are on the data communications loop and uploading a program having an optimization specific to the number of nodes.

Abstract: Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central processor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access time. In one embodiment, the primary systems of the disk emulator are a 66-bit shift register, a parity circuit, a latch circuit, a 66-bit parallel bus and a dynamic random access memory (DRAM) array. Each of these systems interface with control systems of the disk emulator which provide the signals required for the read and write operations of the disk emulator. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit.

Abstract: Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit. The error correction process corrects single bit hard errors in a stored digital data word of “n” bits according to the following steps. The process generates a parity bit for the n-bit word according to a predetermined algorithm prior to storing the word. The process then stores the digital data word in a selected storage location and also stores the parity bit. The process retrieves the stored n-bit word from the selected storage location. The process also retrieves the stored parity bit for the n-bit word. Then, the process generates a new parity bit for the retrieved word according to the predetermined algorithm. The new parity bit is compared with the retrieved parity bit.

Abstract: An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a lock size by a logical block number, to obtain the start address for a memory array read or write operation. The dedicated multiplier circuit advantageously provides very quick computation of these relatively large numbers, which typically involves a 32 bit by 16 bit multiplication. The multiplier includes a shift register initially holding the logical block number which is shifted a particular number of times, the number of shift pulses representing a value of the block length. The output of the shift register is the desired address.

Abstract: An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a block size by a logical block number, to obtain the start address for a memory array read or write operation. The dedicated multiplier circuit advantageously provides very quick computation of these relatively large numbers, which typically involves a 32 bit by 16 bit multiplication. The multiplier includes a shift register initially holding the logical block number which is shifted a particular number of times, the number of shift pulses representing a value of the block length. The output of the shift register is the desired address.

Abstract: Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central processor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access time. In one embodiment, the disk emulator includes a volatile storage medium, a parallel path, a nonvolatile media and a control circuit. The control circuit can store parallel data received on the parallel path into the nonvolatile media and supply parallel data from the nonvolatile storage media on the parallel path. Moreover, in a first mode of operation the control circuit can store data received from a disk controller at a location in the volatile storage medium and in a second mode of operation, the control circuit can retrieve data from the volatile storage medium and provide the retrieved data to the disk controller.

Abstract: Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central processor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access time. In one embodiment, the primary systems of the disk emulator are a 66-bit shift register, a parity circuit, a latch circuit, a 66-bit parallel bus and a dynamic random access memory (DRAM) array. Each of these systems interface with control systems of the disk emulator which provide the signals required for the read and write operations of the disk emulator. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit.

Abstract: Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central procssor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access ttime. In one embodiment, the primary systems of the disk emulator are a 66-bit shift register, a parity circuit, a latch circuit, a 66-bit parallel bus and a dynamic random access memory (DRAM) array. Each of these systems interface with control systems of the disk emulator which provide the signals required for the read and write operations of the disk emulator. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit.

Abstract: A radio frequency oscillator-modulator for use in a video game includes an oscillator circuit, formed from a first differentially connected, emitter-coupled transistor pair having base/collector cross-coupling, that is dc coupled to the differential inputs of a second differentially connected, emitter-coupled transistor pair that forms the modulator circuit. The modulation signal is applied through a resistance to the connected emitters of the modulator circuit to vary the drive current thereof. The radio frequency oscillator-modulator includes bias circuitry that establishes a low level of operation that provides for great linearity and low R.F. radiation.

Abstract: A radio frequency oscillator-modulator for use in a video game includes a folded metal shield box having a slot on one of its ends with which a similarly slotted printed circuit board containing the oscillator and modulator is mated. Circuitry of the oscillator and modulator provides for great linearity and low R.F. radiation. The slot arrangement provides for effective grounding of the ground metallization of the external portion of the printed circuit board which contains the radio frequency output terminal along with the various input terminals. This portion contains ground metallization which makes very effective electrical contact with the slot of the shield box thus again containing R.F. radiation.

Abstract: A radio frequency oscillator-modulator for use in a video game includes a folded metal shield box having a slot on one of its ends in which a similarly slotted printed circuit board containing the oscillator and modulator is mated with. Circuitry of the oscillator and modulator provides for great linearity and low R.F. radiation. The slot arrangement provides for effective grounding of the ground metallization of the external portion of the printed circuit board which contains the radio frequency output terminal along with the various input terminals. This portion contains ground metallization which makes very effective electrical contact with the slot of the shield box thus again containing R.F. radiation.

Abstract: A chroma generation system provides the six major discrete colors in a NTSC color television system. This is achieved simply and inexpensively by a pair of resonant circuits which shift a fundamental color subcarrier signal by lead and lag relationships to provide yellow and magenta colors, respectively, and also provides the proper magnitudes so that when the vectors are combined, a red signal results. The fundamental color signal when inverted provides the complements of the foregoing colors to thus provide the six different discrete saturated colors.