Patents by Inventor Wade K. Smith
Wade K. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220414016Abstract: A translation lookaside buffer (TLB) receives mapping invalidation requests from one or more sources, such as one or more processing units of a processing system. The TLB includes one or more invalidation processing pipelines, wherein each processing pipeline includes multiple processing states arranged in a pipeline, so that a given stage executes its processing operations concurrent with other stages of the pipeline executing their processing operations.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Inventors: Wade K. Smith, Anthony Asaro
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Patent number: 10417140Abstract: Techniques are provided for using a translation lookaside buffer to provide low latency memory address translations for data streams. Clients of a memory system first prepare the address translation cache hierarchy by requesting that a translation pre-fetch stream is initialized. After the translation pre-fetch stream is initialized, the cache hierarchy returns an acknowledgment of completion to the client, which then begins to access memory. Pre-fetch streams are specified in terms of address ranges and are performed for large contiguous portions of the virtual memory address space.Type: GrantFiled: February 24, 2017Date of Patent: September 17, 2019Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Wade K. Smith, Kostantinos Danny Christidis
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Patent number: 10365824Abstract: Systems, apparatuses, and methods for migrating memory pages are disclosed herein. In response to detecting that a migration of a first page between memory locations is being initiated, a first page table entry (PTE) corresponding to the first page is located and a migration pending indication is stored in the first PTE. In one embodiment, the migration pending indication is encoded in the first PTE by disabling read and write permissions. If a translation request targeting the first PTE is received by the MMU and the translation request corresponds to a read request, a read operation is allowed to the first page. Otherwise, if the translation request corresponds to a write request, a write operation to the first page is blocked and a silent retry request is generated and conveyed to the requesting client.Type: GrantFiled: April 24, 2017Date of Patent: July 30, 2019Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Wade K. Smith, Anthony Asaro
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Patent number: 10339068Abstract: Systems, apparatuses, and methods for implementing a virtualized translation lookaside buffer (TLB) are disclosed herein. In one embodiment, a system includes at least an execution unit and a first TLB. The system supports the execution of a plurality of virtual machines in a virtualization environment. The system detects a translation request generated by a first virtual machine with a first virtual memory identifier (VMID). The translation request is conveyed from the execution unit to the first TLB. The first TLB performs a lookup of its cache using at least a portion of a first virtual address and the first VMID. If the lookup misses in the cache, the first TLB allocates an entry which is addressable by the first virtual address and the first VMID, and the first TLB sends the translation request with the first VMID to a second TLB.Type: GrantFiled: April 24, 2017Date of Patent: July 2, 2019Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Wade K. Smith, Anthony Asaro
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Patent number: 10114761Abstract: Techniques are provided for managing address translation request traffic where memory access requests can be made with differing quality-of-service levels, which specify latency and/or bandwidth requirements. The techniques involve translation lookaside buffers. Within the translation lookaside buffers, certain resources are reserved for specific quality-of-service levels. More specifically, translation lookaside buffer slots, which store the actual translations, as well as finite state machines in a work queue, are reserved for specific quality-of-service levels. The translation lookaside buffer receives multiple requests for address translation. The translation lookaside buffer selects requests having the highest quality-of-service level for which an available finite state machine is available.Type: GrantFiled: February 24, 2017Date of Patent: October 30, 2018Assignees: ATI TECHNOLOGIES ULC., ADVANCED MICRO DEVICES, INC.Inventors: Wade K. Smith, Kostantinos Danny Christidis
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Publication number: 20180307622Abstract: Systems, apparatuses, and methods for implementing a virtualized translation lookaside buffer (TLB) are disclosed herein. In one embodiment, a system includes at least an execution unit and a first TLB. The system supports the execution of a plurality of virtual machines in a virtualization environment. The system detects a translation request generated by a first virtual machine with a first virtual memory identifier (VMID). The translation request is conveyed from the execution unit to the first TLB. The first TLB performs a lookup of its cache using at least a portion of a first virtual address and the first VMID. If the lookup misses in the cache, the first TLB allocates an entry which is addressable by the first virtual address and the first VMID, and the first TLB sends the translation request with the first VMID to a second TLB.Type: ApplicationFiled: April 24, 2017Publication date: October 25, 2018Inventors: Wade K. Smith, Anthony Asaro
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Publication number: 20180307414Abstract: Systems, apparatuses, and methods for migrating memory pages are disclosed herein. In response to detecting that a migration of a first page between memory locations is being initiated, a first page table entry (PTE) corresponding to the first page is located and a migration pending indication is stored in the first PTE. In one embodiment, the migration pending indication is encoded in the first PTE by disabling read and write permissions. If a translation request targeting the first PTE is received by the MMU and the translation request corresponds to a read request, a read operation is allowed to the first page. Otherwise, if the translation request corresponds to a write request, a write operation to the first page is blocked and a silent retry request is generated and conveyed to the requesting client.Type: ApplicationFiled: April 24, 2017Publication date: October 25, 2018Inventors: Wade K. Smith, Anthony Asaro
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Publication number: 20180300253Abstract: Systems, apparatuses, and methods for implementing a translate further mechanism are disclosed herein. In one embodiment, a processor detects a hit to a first entry of a page table structure during a first lookup to the page table structure. The processor retrieves a page table entry address from the first entry and uses this address to perform a second lookup to the page table structure responsive to detecting a first indication in the first entry. The processor retrieves a physical address from the first entry and uses the physical address to access the memory subsystem responsive to not detecting the first indication in the first entry. In one embodiment, the first indication is a translate further bit being set. In another embodiment, the first indication is a page directory entry as page table entry field not being activated.Type: ApplicationFiled: April 13, 2017Publication date: October 18, 2018Inventors: Wade K. Smith, Anthony Asaro, Dhirendra Partap Singh Rana
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Publication number: 20180246815Abstract: Techniques are provided for managing address translation request traffic where memory access requests can be made with differing quality-of-service levels, which specify latency and/or bandwidth requirements. The techniques involve translation lookaside buffers. Within the translation lookaside buffers, certain resources are reserved for specific quality-of-service levels. More specifically, translation lookaside buffer slots, which store the actual translations, as well as finite state machines in a work queue, are reserved for specific quality-of-service levels. The translation lookaside buffer receives multiple requests for address translation. The translation lookaside buffer selects requests having the highest quality-of-service level for which an available finite state machine is available.Type: ApplicationFiled: February 24, 2017Publication date: August 30, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Wade K. Smith, Kostantinos Danny Christidis
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Publication number: 20180246816Abstract: Techniques are provided for using a translation lookaside buffer to provide low latency memory address translations for data streams. Clients of a memory system first prepare the address translation cache hierarchy by requesting that a translation pre-fetch stream is initialized. After the translation pre-fetch stream is initialized, the cache hierarchy returns an acknowledgment of completion to the client, which then begins to access memory. Pre-fetch streams are specified in terms of address ranges and are performed for large contiguous portions of the virtual memory address space.Type: ApplicationFiled: February 24, 2017Publication date: August 30, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Wade K. Smith, Kostantinos Danny Christidis
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Patent number: 9483412Abstract: A device for and method of storing page table entries in a first cache. A first page table entry is received having a fragment field that contains address information for a requested first page and at least a second page logically adjacent to the first page. A second page table entry is generated from the first page table entry to be stored with the first page table entry. The second page table entry provides address information for the second page. The second page table entry has a configuration that is compatible with the first cache.Type: GrantFiled: October 16, 2014Date of Patent: November 1, 2016Assignee: Advanced Micro Devices, Inc.Inventor: Wade K. Smith
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Publication number: 20150121009Abstract: A device for and method of storing page table entries in a first cache. A first page table entry is received having a fragment field that contains address information for a requested first page and at least a second page logically adjacent to the first page. A second page table entry is generated from the first page table entry to be stored with the first page table entry. The second page table entry provides address information for the second page. The second page table entry has a configuration that is compatible with the first cache.Type: ApplicationFiled: October 16, 2014Publication date: April 30, 2015Inventor: Wade K. Smith
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Publication number: 20150121012Abstract: A device and method for partitioning a cache that is expected to operate with at least two classes of clients (such as real-time clients and non-real-time clients). A first portion of the cache is dedicated to real-time clients such that non-real-time clients are prevented from utilizing said first portion.Type: ApplicationFiled: October 16, 2014Publication date: April 30, 2015Inventor: Wade K. Smith
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Patent number: 8037281Abstract: Described herein are systems and methods that reduce the latency which may occur when a level one (L1) cache issues a request to a level two (L2) cache, and that ensure that a translation requests sent to an L2 cache are flushed during a context switch. Such a system may include a work queue and a cache (such as an L2 cache). The work queue comprises a plurality of state machines, each configured to store a request for access to memory. The state machines can monitor requests that are stored in the other state machines and requests that the other state machines issue to the cache. A state machine only sends its request to the cache if another state machine is not already awaiting translation data relating to the that request. In this way, the request/translation traffic between the work queue and the cache can be significantly reduced.Type: GrantFiled: August 16, 2007Date of Patent: October 11, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Warren F. Kruger, Wade K. Smith
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Patent number: 7539843Abstract: The present invention is directed to a method, computer program product, and system for processing memory access requests. The method includes the following features. First, page table entries of a page table are organized into at least one fragment that maps logical memory to at least one of logical memory or physical memory. The at least one fragment has a fragment size and an alignment boundary. Then, a subset of the page table entries stored in one of a plurality of cache banks is accessed to determine a mapping between a first logical memory address and at least one of a second logical memory address or a physical memory address. Each cache bank is configured to store at least one page table entry corresponding to a fragment of a predetermined set of fragment sizes and a predetermined alignment boundary.Type: GrantFiled: October 13, 2006Date of Patent: May 26, 2009Assignee: ATI Technologies, Inc.Inventors: Warren F. Kruger, Wade K. Smith
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Patent number: 7447869Abstract: A method and apparatus for fragment processing in a virtual memory system are described. Embodiments of the invention include a coprocessor comprising a virtual memory system for accessing a physical memory. Page table logic and fragment processing logic scan a page table having a fixed, relatively small page size. The page table is broken into fragments made up of pages that are contiguous in physical address space and logical address space and have similar attributes. Fragments in logical address space begin on known boundaries such that the boundary indicates both a starting address of a fragment and the size of the fragment. Corresponding fragments in physical address space can begin anywhere, thus making the process transparent to physical memory. A fragment field in a page table entry conveys both fragment size and boundary information.Type: GrantFiled: April 7, 2005Date of Patent: November 4, 2008Assignee: ATI Technologies, Inc.Inventors: W. Fritz Kruger, Wade K Smith, Robert A. Drebin
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Patent number: 6424345Abstract: A method for rendering polygons in a computer graphics system in which the computer display is divided into a plurality of subregions, and the rasterization process is performed in a micro framebuffer for each subregion, rather than sending raster data for each triangle into the frame buffer. Each polygon undergoes a first stage bounding box intersection test to identify the subregions which are likely to intersect with the polygon. If the number or configuration of intersected subregions exceeds a predetermined threshold requirement, then the polygon undergoes a more precise second stage intersection test to identify which subregions are actually intersected by the polygon. If the number or configuration of intersected subregions is below the threshold requirement, then the control data for the polygon is passed on to each of the identified subregions.Type: GrantFiled: October 14, 1999Date of Patent: July 23, 2002Assignee: ATI International SRLInventors: Wade K. Smith, James T. Battle, Chris J. Goodman
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Patent number: 5982373Abstract: A method of rendering 3-D graphical image data suitable for use in interactive 3-D applications is provided, which reduces the amount of time required to perform the rendering. This is achieved by dynamically adjusting the resolution of the image depending upon the type of operation being performed. 3-D operations are performed at a reduced resolution, while 2-D operations (including display) are performed at full resolution. A method of dynamically enhancing/reducing resolution for image depth information (z-buffer data) is also provided.Type: GrantFiled: November 12, 1996Date of Patent: November 9, 1999Assignee: Chromatic Research, Inc.Inventors: Jennifer F. Inman, Wade K. Smith, Sanford S. Lum
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Patent number: 5949439Abstract: A software queue located in an offscreen portion of video memory is used as a large-capacity software queue for queuing messages to a graphics accelerator. Although the software queue is typically stored in a dynamic RAM (DRAM) memory, advantages of faster static RAM (SRAM) are achieved by shadowing some of the queuing information in SRAM. Usage of a large-capacity software queue in video DRAM memory and information shadowing in faster SRAM memory achieves an advantageous balance between throughput speed and queue size. The large-capacity of the software queue ensures that the queue is virtually never filled to capacity so that delays while awaiting free space in the queue are virtually never incurred. The capacity of the software queue is determined in software and is therefore adaptable to match a particular graphics application.Type: GrantFiled: August 15, 1996Date of Patent: September 7, 1999Assignee: Chromatic Research, Inc.Inventors: Roey Ben-Yoseph, Paul Hsieh, Wade K. Smith