Abstract: A method and apparatus are described for adjusting a bit width of an input/output (I/O) link established between a transmitter and a receiver. The I/O link has a plurality of bit lanes. The transmitter may send to the receiver a command identifying at least one selected bit lane of the I/O link that will be powered off or powered on in response to detecting that a bit width adjustment threshold of the I/O link has been reached.

Abstract: When odorant injection systems are inactive, they may accumulate unwanted vapors in the pump mechanism and associated tubing. In order to restart the odorant injection system, it is best to purge the unwanted vapors from the odorant pumps. The present pump purge system facilitates purging of unwanted vapors from odorant injection systems in an environmentally friendly fashion. The pump purge system purifies these vapors before they are vented to atmosphere. In addition, the pump purge system accumulates liquid odorant which is a byproduct of the purging process and stores it in a tank to reduce the likelihood of improper disposal. As an option, the pump purge system may also include a liquid odorant recapture system. The liquid odorant recapture system uses high pressure gas to return accumulated liquid odorant to the odorant injection system to be reused. This liquid odorant recovery system ensures environmentally responsible behavior.

Abstract: A device and method for transferring data is disclosed that facilitates data transfers between devices having different clock domains. The data transfer from one device to another occurs through a First In First Out memory (FIFO). The relative number of FIFO access cycles to the FIFO is controlled to maintain a desired FIFO fullness. Setting the desired FIFO fullness to a desired value allows control of data transfer latency between devices.

Abstract: When odorant injection systems are inactive, they may accumulate unwanted vapors in the pump mechanism and associated tubing. In order to restart the odorant injection system, it is best to purge the unwanted vapors from the odorant pumps. The present pump purge system facilitates purging of unwanted vapors from odorant injection systems in an environmentally friendly fashion. The pump purge system purifies these vapors before they are vented to atmosphere. In addition, the pump purge system accumulates liquid odorant which is a byproduct of the purging process and stores it in a tank to reduce the likelihood of improper disposal. As an option, the pump purge system may also include a liquid odorant recapture system. The liquid odorant recapture system uses high pressure gas to return accumulated liquid odorant to the odorant injection system to be reused. This liquid odorant recovery system ensures environmentally responsible behavior.

Abstract: The apparatus and method for venting and depressurization of an odorant injection system may be used on special LNG tankers that have onboard gasification equipment, on land or elsewhere. Odorant injection systems may operate at high pressures on an intermittent basis. On some occasions, the odorant is drained from a pressurized system and disposed of in inappropriate ways. The present invention depressurizes an odorant injection system and transfers the unwanted liquid odorant back into an odorant tank where it can be reused when the odorant injection system is restarted.

Abstract: A device and method for transferring data is disclosed that facilitates data transfers between devices having different clock domains. The data transfer from one device to another occurs through a First In First Out memory (FIFO). The relative number of FIFO access cycles to the FIFO is controlled to maintain a desired FIFO fullness. Setting the desired FIFO fullness to a desired value allows control of data transfer latency between devices.

Abstract: A device and method for transferring data is disclosed that facilitates data transfers between devices having different clock domains. The data transfer from one device to another occurs through a First In First Out memory (FIFO). The relative number of FIFO access cycles to the FIFO is controlled to maintain a desired FIFO fullness. Setting the desired FIFO fullness to a desired value allows control of data transfer latency between devices.

Abstract: Data transfer between different clock domains occurs through a FIFO. The relative number of read and write FIFO access cycles to the FIFO is controlled to maintain a desired latency.

Abstract: A microcontroller integrates an internal memory accessible by the cores included thereon. Logic within the microcontroller compares memory addresses generated by the cores to values in a configuration register specifying a memory address range in which the internal memory resides. The logic generates a chip select signal to the internal memory if the memory address generated resides within the specified address range to enable accesses by the cores to the internal memory. The integrated circuit may be configured in a debug mode wherein the chip select signal is inhibited to the internal memory, however the chip select signal is provided external to the integrated circuit on a pin. The chip select signal may then be used to select an external memory which serves to overlay the internal memory address range. Thus the debug mode allows instruction code and data to reside in the external memory rather than the internal memory while in the debug mode.