Abstract: Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.

Abstract: A fabric control protocol (FCP) and packet forwarding mechanisms are described that maximize utilization of bandwidth within massive, large-scale data centers having multi-stage data center switch fabric topologies, such as topologies that include a third switching layer formed by super spine switches. Automatic generation of data plane forwarding information referred to as FCP path information enumerates, for each data processing unit (DPU), the available FCP paths. The FCP path information may be based on unique combinations of peak points of the switch fabric for a given DPU with FCP colors assigned to network links that are used to multi-home the DPU to the switch fabric.

Abstract: Techniques are described for providing a scaled-out transport supported by interconnected data processing units (DPUs) that operates as a single system bus connection proxy for device-to-device communications within a data center. As one example, this disclosure describes techniques for providing a Peripheral Component Interconnect Express (PCIe) proxy for device-to-device communications employing the PCIe standard. The disclosed techniques include adding PCIe proxy logic on top of a host unit of a DPU to expose a PCIe proxy model to application processors, storage devices, network interface controllers, field programmable gate arrays, or other PCIe endpoint devices. The PCIe proxy model may be implemented as a physically distributed Ethernet-based switch fabric with PCIe proxy logic at the edge and fronting the PCIe endpoint devices. The interconnected DPUs and the distributed Ethernet-based switch fabric together provide a reliable, low-latency, and scaled-out transport that operates as a PCIe proxy.

Abstract: Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.

Abstract: Timer management techniques are described. An example processing device includes a memory configured to store successive wheels available to be included in traversal paths for timers running on the device, each wheel representing a queue of timers, each wheel having a different, corresponding time delay (TO) value for queuing a timer, and processing circuitry in communication with the memory. The processing circuitry is configured to determine, in response to a request for a timer, a total traversal time for the timer, to select, from the stored wheels, a subset of wheels such that a sum of the respective TO values of the selected subset is within a predetermined margin of error with respect to the total traversal time for the timer, and to sequence the selected subset of wheels based on the respective TO values of the selected subset of wheels to form a traversal path for the timer.

Abstract: Network access node virtual fabrics configured dynamically over an underlay network are described. A centralized controller, such as a software-defined networking (SDN) controller, of a packet switched network is configured to establish one or more virtual fabrics as overlay networks on top of the physical underlay network of the packet switched network. For example, the SDN controller may define multiple sets of two of more access nodes connected to the packet switched network, and the access nodes of a given one of the sets may use a new data transmission protocol, referred to generally herein as a fabric control protocol (FCP), to dynamically setup tunnels as a virtual fabric over the packet switched network. The FCP tunnels may include all or a subset of the parallel data paths through the packet switched network between the access nodes for a given virtual fabric.

Abstract: A network adaptor (or NIC) is equipped with multi-level protocol processing capability and is implemented with a protocol processing pipeline that has multiple tap points to enable the integration of co-processors to operate with the NIC. The capability leverages the protocol processing pipeline and all the existing NIC software while at the same time enabling the integration of value added co-processors to customize and enhance the NIC capabilities.

Abstract: Network access node virtual fabrics configured dynamically over an underlay network are described. A centralized controller, such as a software-defined networking (SDN) controller, of a packet switched network is configured to establish one or more virtual fabrics as overlay networks on top of the physical underlay network of the packet switched network. For example, the SDN controller may define multiple sets of two of more access nodes connected to the packet switched network, and the access nodes of a given one of the sets may use a new data transmission protocol, referred to generally herein as a fabric control protocol (FCP), to dynamically setup tunnels as a virtual fabric over the packet switched network. The FCP tunnels may include all or a subset of the parallel data paths through the packet switched network between the access nodes for a given virtual fabric.

Abstract: Techniques are described in which a device, such as a network device, compute node or storage device, is configured to utilize a work unit (WU) stack data structure in a multiple core processor system to help manage an event driven, run-to-completion programming model of an operating system executed by the multiple core processor system. The techniques may be particularly useful when processing streams of data at high rates. The WU stack may be viewed as a stack of continuation work units used to supplement a typical program stack as an efficient means of moving the program stack between cores. The work unit data structure itself is a building block in the WU stack to compose a processing pipeline and services execution. The WU stack structure carries state, memory, and other information in auxiliary variables.

Abstract: A new processing architecture is described that utilizes a data processing unit (DPU). Unlike conventional compute models that are centered around a central processing unit (CPU), the DPU that is designed for a data-centric computing model in which the data processing tasks are centered around the DPU. The DPU may be viewed as a highly programmable, high-performance I/O and data-processing hub designed to aggregate and process network and storage I/O to and from other devices. The DPU comprises a network interface to connect to a network, one or more host interfaces to connect to one or more application processors or storage devices, and a multi-core processor with two or more processing cores executing a run-to-completion data plane operating system and one or more processing cores executing a multi-tasking control plane operating system. The data plane operating system is configured to support software functions for performing the data processing tasks.

Abstract: A network system for a data center is described in which an access node sprays a data flow of packets over a logical tunnel to another access node. In one example, a method comprises establishing, by a plurality of access nodes, a logical tunnel over a plurality of data paths across a switch fabric between a source access node and a destination access node included within the plurality of access nodes, wherein the source access node is coupled to a source network device; and spraying, by the source access node, a data flow of packets over the logical tunnel to the destination access node, wherein the source access node receives the data flow of packets from the source network device, and wherein spraying the data flow of packets includes directing each of the packets within the data flow to a least loaded data path.

Abstract: An access node that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from network devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to receive data to be processed, wherein the access node includes a plurality of processing cores, a data network fabric, and a control network fabric; receive, over the control network fabric, a work unit message indicating a processing task to be performed a processing core; and process the work unit message, wherein processing the work unit message includes retrieving data associated with the work unit message over the data network fabric.

Abstract: A new processing architecture is described that utilizes a data processing unit (DPU). Unlike conventional compute models that are centered around a central processing unit (CPU), the DPU that is designed for a data-centric computing model in which the data processing tasks are centered around the DPU. The DPU may be viewed as a highly programmable, high-performance I/O and data-processing hub designed to aggregate and process network and storage I/O to and from other devices. The DPU comprises a network interface to connect to a network, one or more host interfaces to connect to one or more application processors or storage devices, and a multi-core processor with two or more processing cores executing a run-to-completion data plane operating system and one or more processing cores executing a multi-tasking control plane operating system. The data plane operating system is configured to support software functions for performing the data processing tasks.

Abstract: A network system for a data center is described in which a switch fabric provides full mesh interconnectivity such that any servers may communicate packet data to any other of the servers using any of a number of parallel data paths. Moreover, according to the techniques described herein, edge-positioned access nodes, optical permutation devices and core switches of the switch fabric may be configured and arranged in a way such that the parallel data paths provide single L2/L3 hop, full mesh interconnections between any pairwise combination of the access nodes, even in massive data centers having tens of thousands of servers.

Abstract: Methods and apparatus for memory management are described. In one example, this disclosure describes a method that includes executing, by a first processing unit, first work unit operations specified by a first work unit message, wherein execution of the first work unit operations includes accessing data from shared memory included within the computing system, modifying the data, and storing the modified data in a first cache associated with the first processing unit; identifying, by the computing system, a second work unit message that specifies second work unit operations that access the shared memory; updating, by the computing system, the shared memory by storing the modified data in the shared memory; receiving, by the computing system, an indication that updating the shared memory with the modified data is complete; and enabling the second processing unit to execute the second work unit operations.

Abstract: A fabric control protocol is described for use within a data center in which a switch fabric provides full mesh interconnectivity such that any of the servers may communicate packet data for a given packet flow to any other of the servers using any of a number of parallel data paths within the data center switch fabric. The fabric control protocol enables spraying of individual packets for a given packet flow across some or all of the multiple parallel data paths in the data center switch fabric and, optionally, reordering of the packets for delivery to the destination. The fabric control protocol may provide end-to-end bandwidth scaling and flow fairness within a single tunnel based on endpoint-controlled requests and grants for flows. In some examples, the fabric control protocol packet structure is carried over an underlying protocol, such as the User Datagram Protocol (UDP).

Abstract: A highly-programmable access node is described that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from storage devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to execute a large number of data I/O processing tasks relative to a number of instructions that are processed. The access node may be highly programmable such that the access node may expose hardware primitives for selecting and programmatically configuring data processing operations. As one example, the access node may be used to provide high-speed connectivity and I/O operations between and on behalf of computing devices and storage components of a network, such as for providing interconnectivity between those devices and a switch fabric of a data center.

Abstract: Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.

Abstract: Timer management techniques are described. An example processing device includes a memory configured to store successive wheels available to be included in traversal paths for timers running on the device, each wheel representing a queue of timers, each wheel having a different, corresponding time delay (TO) value for queuing a timer, and processing circuitry in communication with the memory. The processing circuitry is configured to determine, in response to a request for a timer, a total traversal time for the timer, to select, from the stored wheels, a subset of wheels such that a sum of the respective TO values of the selected subset is within a predetermined margin of error with respect to the total traversal time for the timer, and to sequence the selected subset of wheels based on the respective TO values of the selected subset of wheels to form a traversal path for the timer.

Abstract: Methods and apparatus for memory management are described. In a disclosed embodiment, a system has a first and a second processor, with each processor able to access a memory system. A first work unit is received for execution by the first processor, with the memory system being accessed. A second work unit is generated for execution by a second processor upon execution of a first work unit. Only after the memory system is updated does processing of the second work unit by the second processor occur. This work unit message based ordering provides relay consistency for memory operations of multiple processors.