Abstract: Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.

Abstract: A microelectronic package can include a substrate having first and second opposed surfaces extending in first and second transverse directions and an opening extending between the first and second surfaces and defining first and second distinct parts each elongated along a common axis extending in the first direction, first and second microelectronic elements each having a front surface facing the first surface of the substrate and a column of contacts at the respective front surface, a plurality of terminals exposed at the second surface, and first and second electrical connections aligned with the respective first and second parts of the opening and extending from at least some of the contacts of the respective first and second microelectronic elements to at least some of the terminals. The column of contacts of the first and second microelectronic elements can be aligned with the respective first and second parts of the opening.

Abstract: Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.

Abstract: A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.

Abstract: A microelectronic assembly can be made by forming a redistribution structure supported on a carrier, the structure including two or more layers of deposited dielectric material and two or more electrically conductive layers and including conductive features such as pads and traces electrically interconnected by vias. Electrical connectors may project above a second surface of the structure opposite an interconnection surface of the redistribution structure adjacent to the carrier. A microelectronic element may be attached and electrically connected with conductive features at the second surface, and a dielectric encapsulation can be formed contacting the second surface and surfaces of the microelectronic element. Electrically conductive features at the interconnection surface can be configured for connection with corresponding features of a first external component, and the electrical connectors can be configured for connection with corresponding features of a second external component.

Abstract: A method is disclosed of fabricating a microelectronic package comprising a substrate overlying the front face of a microelectronic element. A plurality of metal bumps project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. The metal bumps can be wire bonds having first and second ends attached to a same conductive pad of the substrate. A conductive matrix material contacts at least portions of the lateral surfaces of respective ones of the metal bumps and joins the metal bumps with contacts of the microelectronic element.

Abstract: A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later.

Abstract: A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane.

Abstract: An apparatus relates generally to a microelectromechanical system component. In such an apparatus, the microelectromechanical system component has a lower surface, an upper surface, first side surfaces, and second side surfaces. Surface area of the first side surfaces is greater than surface area of the second side surfaces. The microelectromechanical system component has a plurality of wire bond wires attached to and extending away from a first side surface of the first side surfaces. The wire bond wires are self-supporting and cantilevered with respect to the first side surface of the first side surfaces.

Abstract: A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.

Abstract: A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals.

Abstract: A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A microelectronic package may include a substrate having first and second regions, a first surface and a second surface remote from the first surface; at least one microelectronic element overlying the first surface within the first region; electrically conductive elements at the first surface within the second region; a support structure having a third surface and a fourth surface remote from the third surface and overlying the first surface within the second region in which the third surface faces the first surface, second and third electrically conductive elements exposed respectively at the third and fourth surfaces and electrically connected to the conductive elements at the first surface in the first region; and wire bonds defining edge surfaces and having bases electrically connected through ones of the third conductive elements to respective ones of the second conductive elements and ends remote from the support structure and the bases.

Abstract: An apparatus, and methods therefor, relates generally to an integrated circuit package. In such an apparatus, a platform substrate has a copper pad. An integrated circuit die is coupled to the platform substrate. A wire bond wire couples a contact of the integrated circuit die and the copper pad. A first end of the wire bond wire is ball bonded with a ball bond for direct contact with an upper surface of the copper pad. A second end of the wire bond wire is stitch bonded with a stitch bond to the contact.

Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Abstract: An apparatus relates generally to a microelectromechanical system component. In such an apparatus, the microelectromechanical system component has a lower surface, an upper surface, first side surfaces, and second side surfaces. Surface area of the first side surfaces is greater than surface area of the second side surfaces. The microelectromechanical system component has a plurality of wire bond wires attached to and extending away from a first side surface of the first side surfaces. The wire bond wires are self-supporting and cantilevered with respect to the first side surface of the first side surfaces.

Abstract: A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.

Abstract: A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

Abstract: A microelectronic assembly includes a dielectric element having first and second surfaces, first and second apertures extending between the first and second surfaces and defining a central region of the first surface between the first and second apertures, first and second microelectronic elements, and leads extending from contacts exposed at respective front surfaces of the first and second microelectronic elements to central terminals exposed at the central region. The front surface of the first microelectronic element can face the second surface of the dielectric element. The front surface of the second microelectronic element can face a rear surface of the first microelectronic element. The contacts of the second microelectronic element can project beyond an edge of the first microelectronic element. At least first and second ones of the leads can electrically interconnect a first central terminal of the central terminals with each of the first and second microelectronic elements.