Patents by Inventor Wah S. Wong
Wah S. Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Wide-band transparent electrical contacts and interconnects for FPAS and a method of making the same
Patent number: 9640680Abstract: An optical device includes an optically transparent and electrically conducting conductor including graphene, a network of metal nanowires, or graphene integrated with a network of metal nanowires. The optical device includes a II VI compound semiconductor, a III V compound semiconductor, or InAsSb.Type: GrantFiled: February 18, 2014Date of Patent: May 2, 2017Assignee: HRL Laboratories, LLCInventors: Kyung-Ah Son, Hasan Sharifi, Jeong-Sun Moon, Wah S. Wong, Hwa Chang Seo -
Patent number: 9190534Abstract: A method of fabricating a normally “off” GaN heterostructure field effect transistor having a source and a drain including depositing a passivation layer patterned to cover a channel region between a source and a drain, forming a first opening in the passivation layer, the first opening for defining a gate area in the channel region and the first opening having a first length dimension along a direction of current flow between the source and the drain, and implanting ions in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension.Type: GrantFiled: April 9, 2014Date of Patent: November 17, 2015Assignee: HRL Laboratories, LLCInventors: Tahir Hussain, Miroslav Micovic, Wah S. Wong, Shawn D. Burnham
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Patent number: 8728884Abstract: A method of fabricating a normally “off” GaN heterostructure field effect transistor having a source and a drain including depositing a passivation layer patterned to cover a channel region between a source and a drain, forming a first opening in the passivation layer, the first opening for defining a gate area in the channel region and the first opening having a first length dimension along a direction of current flow between the source and the drain, and implanting ions in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension.Type: GrantFiled: July 28, 2009Date of Patent: May 20, 2014Assignee: HRL Laboratories, LLCInventors: Tahir Hussain, Miroslav Micovic, Wah S. Wong, Shawn D. Burnham
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Patent number: 8368119Abstract: A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting structure, are disclosed. Integration of vertical junction Schottky diodes is enabled, and the parasitic capacitance and resistance as well as the physical size of the diode are minimized. A process for fabricating an integrated group III nitride structure comprising double-heterostructure field effect transistors (DHFETs) and Schottky diodes and the resulting structure are also disclosed.Type: GrantFiled: May 19, 2011Date of Patent: February 5, 2013Assignee: HRL Laboratories, LLCInventors: Louis Luh, Keh-Chung Wang, Wah S. Wong, Miroslav Micovic, David Chow, Don Hitko
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Patent number: 7989277Abstract: A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting structure, are disclosed. Integration of vertical junction Schottky diodes is enabled, and the parasitic capacitance and resistance as well as the physical size of the diode are minimized. A process for fabricating an integrated group III nitride structure comprising double-heterostructure field effect transistors (DHFETs) and Schottky diodes and the resulting structure are also disclosed.Type: GrantFiled: September 11, 2007Date of Patent: August 2, 2011Assignee: HRL Laboratories, LLCInventors: Louis Luh, Keh-Chung Wang, Wah S. Wong, Miroslav Micovic, David Chow, Don Hitko
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Patent number: 7514759Abstract: A process for fabricating a combined micro electromechanical/gallium nitride structure. The micro electromechanical structure comprises a piezoelectric device, such as a piezoelectric switch or a bulk acoustic wave device. According to the process, high Q compact bulk acoustic wave resonators can be built. The process is applicable to technologies such as tunable planar filter technology, amplifier technology and high speed analog-to-digital converters.Type: GrantFiled: April 11, 2005Date of Patent: April 7, 2009Assignee: HRL Laboratories, LLCInventors: Sarabjit Mehta, David E. Grider, Wah S. Wong
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Patent number: 7247893Abstract: A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.Type: GrantFiled: September 1, 2004Date of Patent: July 24, 2007Assignee: HRL Laboratories, LLCInventors: Jeong Sun Moon, Paul Hashimoto, Wah S. Wong, David E. Grider
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Patent number: 6830945Abstract: A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.Type: GrantFiled: March 12, 2003Date of Patent: December 14, 2004Assignee: HRL Laboratories, LLCInventors: Jeong Sun Moon, Paul Hashimoto, Wah S. Wong, David E. Grider
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Publication number: 20040051112Abstract: A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.Type: ApplicationFiled: March 12, 2003Publication date: March 18, 2004Applicant: HRL LABORATORIES, LLCInventors: Jeong Sun Moon, Paul Hashimoto, Wah S. Wong, David E. Grider
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Publication number: 20040021152Abstract: The present invention utilizes the strong piezoelectric effect, found in group-III nitride materials to circumvent the need to selectively remove Gallium Nitride (GaN) in the fabrication of GaN/AlGaN Heterostructure Field Effect Transistors. The transistor is comprised of a semi-insulating substrate 300, a buffer layer 302 which is in continual contact with the semi-insulating substrate 300. A GaN active channel 304 is atop the buffer layer 302. An AlGaN barrier 306 in laid on top of, and is in continual contact with, the GaN active channel 304. Thereafter, there is a source contact 308 and a drain contact 310 both in physical contact with the GaN active channel 308. There is a gate 312 upon the AlGaN barrier 306 and between the source contact 308 and a drain contact 310. At least one dielectric stressor 314 is placed upon the AlGaN barrier 306. The dielectric stressors 314 are between the gate 312 and the source 308 and drain 310 contacts.Type: ApplicationFiled: August 5, 2002Publication date: February 5, 2004Inventors: Chanh Nguyen, Jeong-Sun Moon, Wah S. Wong, Miro Micovic, Paul Hashimoto
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Patent number: 5998817Abstract: A multicell transistor for use in a circuit has an input ground plane for an input waveguide and an output ground plane for an output waveguide. The multicell transistor includes a gate electrode coupled to the input waveguide, a drain electrode coupled to the output waveguide, and a source electrode coupled to the input ground plane. An output ground strap spaced from the drain electrode couples the output ground plane to the source electrode. A pair of transmission lines are orthogonally connected to and extend from the gate electrode to form a pair of inductors for matching the impedances of the gate electrode and the input waveguide.Type: GrantFiled: November 3, 1997Date of Patent: December 7, 1999Assignee: Raytheon CompanyInventors: Cheng P. Wen, Peter Chu, Michael R. Cole, Wah S. Wong, Robert F. Wang, Liping D. Hou
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Patent number: 5877560Abstract: A monolithic flip chip microwave integrated circuit module formed using titanium coated copper circuitry and a processing method. A dam is formed on a substrate by forming a thin protective layer such as titanium or other metal on a copper layer formed on a surface of the substrate to which a monolithic microwave integrated circuit is to be attached. The protective layer is oxidized upon exposure to air. Vias or openings are then formed in the oxidized protective layer. Solder is disposed in the openings in the oxidized protective layer, and is confined to the openings while solder is reflowed to attach the integrated circuit to the substrate. The oxidized protective layer serves a dual function that provides both a solder dam and a protective coating for the underlying copper circuitry. Copper surfaces not covered by the oxidized protective layer may be environmentally protected by depositing a thin layer containing electroless plated nickel and electroless plated gold.Type: GrantFiled: February 21, 1997Date of Patent: March 2, 1999Assignee: Raytheon CompanyInventors: Cheng P. Wen, Kuo-Hsin Li, Wah S. Wong
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Patent number: 5861341Abstract: A thin film (at least one atomic layer to about 400 .ANG.) of nickel is electrolytically plated on top of electrolytically-plated gold electrodes in GaAs monolithic microwave integrated circuits (MMICs) without any additional photoresist masking step. The thin electrolytically-plated nickel film improves adhesion of a passivating dielectric layer (e.g., silicon dioxide, silicon nitride, and silicon oxynitride) formed on the electrolytically-plated gold electrodes. The electrolytically-plated nickel film can be removed locally to facilitate the fabrication of plated silver bumps (for off-chip electrical connections and thermal paths) on passivated flip chip MMICs.Type: GrantFiled: July 15, 1996Date of Patent: January 19, 1999Assignee: Raytheon CompanyInventors: Cheng P. Wen, Wah S. Wong, Arlene E. Arthur
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Patent number: 5773897Abstract: Mushroom-shaped, solder-capped, small-diameter (approximately 50 to 75 microns or less), metal bumps are used in the flip chip monolithic microwave integrated circuits (MMICs) attachment process to provide devices having improved solder volume uniformity. The operation of the MMIC device is extended to millimeter-wave frequencies. The self-alignment property of the solder reflow flip chip attachment process is retained, and enhanced by the solder cap that extends beyond the periphery of the metal bump. Solder flux instead of solder paste patterns are printed on the assembly substrate to facilitate flip chip attachment. The metal bumps comprise electroplated silver pillars having a first diameter capped with electroplated solder having a second diameter, where the second diameter is larger than the first diameter, and are formed using a multi-layer negative photoresist, multiple exposure processing sequence.Type: GrantFiled: February 21, 1997Date of Patent: June 30, 1998Assignee: Raytheon CompanyInventors: Cheng P. Wen, Wah S. Wong
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Patent number: 5708283Abstract: A high power, flip-chip microwave monolithic integrated circuit (MMIC) assembly (30) has a high power microwave monolithic integrated circuit (MMIC) having a surface with an active area (72) in which heat is generated. The assembly also has a host substrate (34). A thermally conductive bump (51) formed over the surface of the MMIC has a first portion (51') in close proximity to and in thermal communication with the active area (72) of the MMIC and a second portion (51") which is in close proximity to and in thermal communication with the host substrate (34). The second portion (51") of the thermal bump (51) has a greater cross-sectional area than the first portion (51'). A multi-layer, multi-exposure method of manufacturing the improved thermal bump (51) includes several steps. A plating membrane (80) is formed on a surface of the MMIC (32). A first layer of negative photoresist is applied to the surface of the plating membrane (80), and is exposed with a first masked pattern of light.Type: GrantFiled: December 20, 1996Date of Patent: January 13, 1998Assignee: Hughes AircraftInventors: Cheng P. Wen, Wah S. Wong, William D. Gray
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Patent number: 5616517Abstract: A high power, flip-chip microwave monolithic integrated circuit (MMIC) assembly (30) has a high power microwave monolithic integrated circuit (MMIC) having a surface with an active area (72) in which heat is generated. The assembly also has a host substrate (34). A thermally conductive bump (51) formed over the surface of the MMIC has a first portion (51') in close proximity to and in thermal communication with the active area (72) of the MMIC and a second portion (51") which is in close proximity to and in thermal communication with the host substrate (34). The second portion (51") of the thermal bump (51) has a greater cross-sectional area than the first portion (51'). A multi-layer, multi-exposure method of manufacturing the improved thermal bump (51) includes several steps. A plating membrane (80) is formed on a surface of the MMIC (32). A first layer of negative photoresist is applied to the surface of the plating membrane (80), and is exposed with a first masked pattern of light.Type: GrantFiled: March 15, 1996Date of Patent: April 1, 1997Assignee: Hughes Aircraft CompanyInventors: Cheng P. Wen, Wah S. Wong, William D. Gray
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Patent number: 5514838Abstract: An integrated circuit assembly that prevents silver migration by providing conductive rims around oxidizable silver contacts that contact a substrate. Typically the silver contacts are supported by respective metal pads on the substrate with a contact potential existing at each contact-pad junction. In many applications an electrical circuit transmits electrical signals via the contacts to produce potential differences between the contacts and create electrical fields at their surfaces. The conductive rims have a work function that is sufficiently small to reduce the electric fields and contact potentials so as to inhibit the ionization of the oxidized contacts' surfaces and prevent silver migration across the metal pads and the substrate.Type: GrantFiled: September 27, 1994Date of Patent: May 7, 1996Assignee: Hughes Aircraft CompanyInventors: Cheng P. Wen, Wah S. Wong, Min-Wen Chiang
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Patent number: 4855796Abstract: A beam lead diode configuration is described, employing a planar proton bombarded conversion region and a low-permittivity dielectric separator. The diode enjoys the mechanical ruggedness of the conventional planar diodes and the electrical performance of conventional mesa-type diodes. The diode structure results in the absence of N-type mesa structures on the substrate, allowing fabrication by relatively low-cost, high-yield photolithographic processes.Type: GrantFiled: June 6, 1986Date of Patent: August 8, 1989Assignee: Hughes Aircraft CompanyInventors: Wah S. Wong, Cheng P. Wen, Jen K. Kung
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Patent number: 4800420Abstract: A two-terminal semiconductor diode device and method for manufacturing the same is disclosed. The semiconductor diode geometry is defined by mesa etching. An ohmic contact is disposed on the flat topped summit of the mesa and another ohmic contact in the shape of a ring is disposed on the bottom layer of the diode. A dielectric layer disposed over the diode has a via hole therethrough to make external contact to a metallic heat sink and ground. A substrate layer supports the semiconductor diode and has a second offset via hole therethrough to the ring contact for external circuit contact and biasing of the diode.The offset via hole simplifies the manufacturing process. Additionally, the active area of the diode makes direct contact to the heat sink improving heat transfer from the device.Type: GrantFiled: May 14, 1987Date of Patent: January 24, 1989Assignee: Hughes Aircraft CompanyInventors: James C. Chen, Wah S. Wong, Cheng K. Pao