Patents by Inventor Wahei Kitamura

Wahei Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7785986
    Abstract: To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: August 31, 2010
    Assignee: Renesas Electronics Corp.
    Inventors: Yoshihisa Matsubara, Hiromichi Suzuki, Wahei Kitamura, Kosho Akiyama, Seiji Kato
  • Publication number: 20090176333
    Abstract: To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.
    Type: Application
    Filed: March 10, 2009
    Publication date: July 9, 2009
    Inventors: Yoshihisa MATSUBARA, Hiromichi Suzuki, Wahei Kitamura, Kosho Akiyama, Seiji Kato
  • Patent number: 7504315
    Abstract: To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: March 17, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yoshihisa Matsubara, Hiromichi Suzuki, Wahei Kitamura, Kosho Akiyama, Seiji Kato
  • Publication number: 20070235371
    Abstract: A method for carrying a semiconductor device includes: (a) providing semiconductor devices each having a main surface, a back surface, and a plurality of external terminals; (b) providing a tray having a front surface, a rear surface, an electronic tag imbedded in the tray, first concaved portions formed on the front surface, second concaved portions formed on the rear surface, the electronic tag constituted by a non-contact recognition type chip having a memory circuit in which recognizable information is stored, a depth of the first concaved portion is deeper than a depth of the second concaved portion; (c) housing the semiconductor devices into the first concaved portions respectively in such a manner that the back surface of the semiconductor device being oppose to a bottom of the first concaved portion; and (d) carrying the tray with the semiconductor devices.
    Type: Application
    Filed: June 8, 2007
    Publication date: October 11, 2007
    Inventors: Hiromichi Suzuki, Wahei Kitamura, Tokuji Toida, Toshimasa Shirai
  • Patent number: 7261207
    Abstract: A method for carrying a semiconductor device includes: (a) providing semiconductor devices each having a main surface, a back surface, and a plurality of external terminals; (b) providing a tray having a front surface, a rear surface, an electronic tag imbedded in the tray, first concaved portions formed on the front surface, second concaved portions formed on the rear surface, the electronic tag constituted by a non-contact recognition type chip having a memory circuit in which recognizable information is stored, a depth of the first concaved portion is deeper than a depth of the second concaved portion; (c) housing the semiconductor devices into the first concaved portions respectively in such a manner that the back surface of the semiconductor device being oppose to a bottom of the first concaved portion; and (d) carrying the tray with the semiconductor devices.
    Type: Grant
    Filed: February 4, 2004
    Date of Patent: August 28, 2007
    Assignees: Renesas Technology Corp., Hitachi Transport System Ltd.
    Inventors: Hiromichi Suzuki, Wahei Kitamura, Tokuji Toida, Toshimasa Shirai
  • Patent number: 6981585
    Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging. To solve this problem, the devices are packaged moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: January 3, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
  • Publication number: 20050147488
    Abstract: To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.
    Type: Application
    Filed: December 9, 2004
    Publication date: July 7, 2005
    Inventors: Yoshihisa Matsubara, Hiromichi Suzuki, Wahei Kitamura, Kosho Akiyama, Seiji Kato
  • Publication number: 20040181938
    Abstract: Clean accommodation and carrying of semiconductor devices are to be attained. A stack type tray is used which comprises a base portion 1d with plural pockets formed therein in a matrix shape and side walls formed along peripheral edges of the base portion. In the tray is buried an electronic tag which is constituted by a mu-chip having memory with non-contact recognizable information stored therein. Information pieces such as ID, manufacturer's name and product number of the tray, as well as product name, quantity and lot number of an object to be accommodated, are stored in the mu-chip of the electronic tag, and by accommodating a to-be-accommodated object in the tray equipped with the mu-chip and carrying it, the generation of dust can be prevented because paper label is not used.
    Type: Application
    Filed: February 4, 2004
    Publication date: September 23, 2004
    Applicants: Renesas Technology Corp, Hitachi Transport System, Ltd.
    Inventors: Hiromichi Suzuki, Wahei Kitamura, Tokuji Toida, Toshimasa Shirai
  • Publication number: 20030057113
    Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging.
    Type: Application
    Filed: July 30, 2002
    Publication date: March 27, 2003
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
  • Publication number: 20020179460
    Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging.
    Type: Application
    Filed: July 30, 2002
    Publication date: December 5, 2002
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
  • Publication number: 20020174627
    Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging.
    Type: Application
    Filed: July 30, 2002
    Publication date: November 28, 2002
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
  • Patent number: 6443298
    Abstract: In surface packaging of thin resin packages such as surface mount resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging. To solve this problem, the devices are sealed, by heat-sealing, in a bag moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging. The devices are packaged in a moisture-proofing bag made of a laminate film, and a desiccant is sealed, by heat-sealing the bag, in the moisture-proofing bag together with the, e.g., surface mount semiconductor device having a plastic package encapsulating the semiconductor device. A caution is provided for the bag, that the devices should be presented from moisture absorption after opening the bag.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: September 3, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
  • Publication number: 20010015327
    Abstract: In surface packaging of thin resin packages such as surface mount resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging. To solve this problem, the devices are sealed, by heat-sealing, in a bag moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging. The devices are packaged in a moisture-proofing bag made of a laminate film, and a desiccant is sealed, by heat-sealing the bag, in the moisture-proofing bag together with the, e.g., surface mount semiconductor device having a plastic package encapsulating the semiconductor device. A caution is provided for the bag, that the devices should be presented from moisture absorption after opening the bag.
    Type: Application
    Filed: April 30, 2001
    Publication date: August 23, 2001
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
  • Patent number: 6223893
    Abstract: In surface packaging of thin resin packages such as surface mount resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging. To solve this problem, the devices are sealed, by heat-sealing, in a bag moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging. The devices are packaged in a moisture-proofing bag made of a laminate film, and a desiccant is sealed, by heat-sealing the bag, in the moisture-proofing bag together with the, e.g., surface mount semiconductor device having a plastic package encapsulating the semiconductor device.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: May 1, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
  • Patent number: 5988368
    Abstract: In surface packaging of thin resin packages such as surface mount resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging. To solve this problem, the devices are sealed in a bag moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging. The devices are packaged in a moisture-proofing bag made of a laminate film, and a desiccant is sealed in the moisture-proofing bag together with the, e.g., surface mount semiconductor device having a plastic package encapsulating the semiconductor device.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: November 23, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
  • Patent number: 5803246
    Abstract: In surface packaging of thin resin packages such as surface mount resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging. To solve this problem, the devices are packaged moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging.
    Type: Grant
    Filed: September 13, 1996
    Date of Patent: September 8, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
  • Patent number: 5607059
    Abstract: In surface packaging of thin resin packages such as resin molded memory ICs cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging. To solve this problem, the devices are packaged moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging.
    Type: Grant
    Filed: June 23, 1994
    Date of Patent: March 4, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
  • Patent number: 5295297
    Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging.To solve this problem, the devices are packaged moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging.
    Type: Grant
    Filed: July 20, 1992
    Date of Patent: March 22, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
  • Patent number: 5274914
    Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging.To solve this problem, the devices are packaged moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging.
    Type: Grant
    Filed: July 20, 1992
    Date of Patent: January 4, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
  • Patent number: 5095626
    Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging.To solve this problem, the devices are packaged moisture-tight at an assembly step of the resin molded devices wherein the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging.
    Type: Grant
    Filed: August 10, 1989
    Date of Patent: March 17, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi