Patents by Inventor Waikin Li
Waikin Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240036470Abstract: A method is provided for forming an interconnect structure for an integrated circuit.Type: ApplicationFiled: July 21, 2023Publication date: February 1, 2024Inventors: Waikin Li, Zheng Tao
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Patent number: 11862452Abstract: In a first aspect, the present disclosure relates to a method for forming a contact isolation for a semiconductor device, comprising: providing a semiconductor structure comprising a trench exposing a contact thereunder, filling a bottom of the trench with a sacrificial material, infiltrating the sacrificial material with a ceramic material, and removing the sacrificial material.Type: GrantFiled: August 28, 2020Date of Patent: January 2, 2024Assignee: IMEC VZWInventors: Boon Teik Chan, Waikin Li, Zheng Tao
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Patent number: 11824122Abstract: A method for partially filling a space between two superimposed structures in a semiconductor device under construction is provided. The method includes the steps of: (a) providing the two superimposed structures having said space therebetween; (b) entirely filling said space with a thermoplastic material; (c) removing a first portion of the thermoplastic material present in the space, the first portion comprising at least part of a top surface of the thermoplastic material, thereby leaving in said space a remaining thermoplastic material having a height; and (d) heating up the remaining photosensitive thermoplastic material so as to reduce its height. A replacement metal gate process for forming a different gate stack on two superimposed transistor channels in a semiconductor device under construction as well as a semiconductor device under construction is also provided.Type: GrantFiled: March 22, 2021Date of Patent: November 21, 2023Assignee: Imec vzwInventors: Boon Teik Chan, Waikin Li, Zheng Tao
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Publication number: 20230207482Abstract: A semiconductor structure includes a device area that includes a first structure in a first layer having a top surface above a top surface of the first layer, and a second structure in a second layer on top of the first layer, where the first structure is pinned in the second structure; an overlay metrology area for optically evaluating an overlay error between the second and first structure, including: a third structure in the first layer, having a top surface above the top surface of the first layer, a fourth structure in the second layer, where the combination of the third and fourth structures mimics the combination of the first structure and the second structures, and a fifth structure in the first layer, for use as a reference structure.Type: ApplicationFiled: December 20, 2022Publication date: June 29, 2023Inventors: Waikin Li, Zheng Tao, Min-Soo Kim
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Publication number: 20230046117Abstract: A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.Type: ApplicationFiled: August 10, 2022Publication date: February 16, 2023Inventors: Zheng Tao, Waikin Li
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Publication number: 20210296500Abstract: A method for partially filling a space between two superimposed structures in a semiconductor device under construction is provided. The method includes the steps of: (a) providing the two superimposed structures having said space therebetween; (b) entirely filling said space with a thermoplastic material; (c) removing a first portion of the thermoplastic material present in the space, the first portion comprising at least part of a top surface of the thermoplastic material, thereby leaving in said space a remaining thermoplastic material having a height; and (d) heating up the remaining photosensitive thermoplastic material so as to reduce its height. A replacement metal gate process for forming a different gate stack on two superimposed transistor channels in a semiconductor device under construction as well as a semiconductor device under construction is also provided.Type: ApplicationFiled: March 22, 2021Publication date: September 23, 2021Inventors: Boon Teik Chan, Waikin Li, Zheng Tao
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Publication number: 20210066116Abstract: In a first aspect, the present disclosure relates to a method for forming a contact isolation for a semiconductor device, comprising: providing a semiconductor structure comprising a trench exposing a contact thereunder, filling a bottom of the trench with a sacrificial material, infiltrating the sacrificial material with a ceramic material, and removing the sacrificial material.Type: ApplicationFiled: August 28, 2020Publication date: March 4, 2021Inventors: Boon Teik Chan, Waikin Li, Zheng Tao
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Patent number: 10818504Abstract: A method for producing a pattern of features on a substrate may involve performing two exposure steps on a resist layer applied to the substrate, followed by a single etching step. In the two exposures, the same pattern of mask features is used, but with possibly differing dimensions and with the pattern applied in the second exposure being shifted in position relative to the pattern in the first exposure. The shift, lithographic parameters, and/or possibly differing dimensions are configured such that a number of resist areas exposed in the second exposure overlap one or more resist areas exposed in the first exposure. When the pattern of mask features is a regular 2-dimensional array, the method produces of an array of holes or pillars that is denser than the original array. Varying the mask patterns can produce different etched structure shapes, such as a zig-zag pattern.Type: GrantFiled: December 13, 2018Date of Patent: October 27, 2020Assignee: IMEC VZWInventors: Waikin Li, Danilo De Simone, Sandip Halder, Frederic Lazzarino
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Publication number: 20190189458Abstract: A method for producing a pattern of features on a substrate may involve performing two exposure steps on a resist layer applied to the substrate, followed by a single etching step. In the two exposures, the same pattern of mask features is used, but with possibly differing dimensions and with the pattern applied in the second exposure being shifted in position relative to the pattern in the first exposure. The shift, lithographic parameters, and/or possibly differing dimensions are configured such that a number of resist areas exposed in the second exposure overlap one or more resist areas exposed in the first exposure. When the pattern of mask features is a regular 2-dimensional array, the method produces of an array of holes or pillars that is denser than the original array. Varying the mask patterns can produce different etched structure shapes, such as a zig-zag pattern.Type: ApplicationFiled: December 13, 2018Publication date: June 20, 2019Applicant: IMEC VZWInventors: Waikin Li, Danilo De Simone, Sandip Halder, Frederic Lazzarino
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Patent number: 10199463Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.Type: GrantFiled: February 27, 2018Date of Patent: February 5, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Waikin Li, Chengwen Pei, Ping-Chuan Wang
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Publication number: 20180190770Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Inventors: Waikin LI, Chengwen PEI, Ping-Chuan WANG
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Patent number: 9966431Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.Type: GrantFiled: March 23, 2016Date of Patent: May 8, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Waikin Li, Chengwen Pei, Ping-Chuan Wang
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Publication number: 20170278927Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.Type: ApplicationFiled: March 23, 2016Publication date: September 28, 2017Inventors: Waikin LI, Chengwen PEI, Ping-Chuan WANG
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Patent number: 6861209Abstract: A method to enhance resolution of a chemically amplified photoresist generally includes forming a relief image in the chemically amplified photoresist, wherein the relief image comprises a feature having a first dimension; and contacting the relief image with an aqueous acidic solution for a period of time effective to reduce first dimension of the relief image to a second dimension.Type: GrantFiled: December 3, 2002Date of Patent: March 1, 2005Assignee: International Business Machines CorporationInventors: Waikin Li, Chung-Hsi Wu
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Publication number: 20040106070Abstract: A method to enhance resolution of a chemically amplified photoresist generally includes forming a relief image in the chemically amplified photoresist, wherein the relief image comprises a feature having a first dimension; and contacting the relief image with an aqueous acidic solution for a period of time effective to reduce first dimension of the relief image to a second dimension.Type: ApplicationFiled: December 3, 2002Publication date: June 3, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Waikin Li, Chung-Hsi Wu