Patents by Inventor Wai-Yeung Yip

Wai-Yeung Yip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070120575
    Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
    Type: Application
    Filed: January 29, 2007
    Publication date: May 31, 2007
    Applicant: Rambus Inc.
    Inventors: Belgacem Haba, Richard Perego, David Nguyen, Billy Garrett, Ely Tsern, Craig Hampel, Wai-Yeung Yip
  • Publication number: 20050142950
    Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
    Type: Application
    Filed: February 11, 2005
    Publication date: June 30, 2005
    Applicant: Rambus Inc.
    Inventors: Belgacem Haba, Richard Perego, David Nguyen, Billy Garrett, Ely Tsern, Craig Hampel, Wai-Yeung Yip
  • Patent number: 6898085
    Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: May 24, 2005
    Assignee: Rambus Inc.
    Inventors: Belgacem Haba, Richard E. Perego, David Nguyen, Billy W. Garrett, Jr., Ely Tsern, Craig E. Hampel, Wai-Yeung Yip
  • Patent number: 6765800
    Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: July 20, 2004
    Assignee: Rambus Inc.
    Inventors: Belgacem Haba, Richard E. Perego, David Nguyen, Billy W. Garrett, Jr., Ely Tsern, Craig E. Hampel, Wai-Yeung Yip
  • Publication number: 20040105240
    Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
    Type: Application
    Filed: October 30, 2003
    Publication date: June 3, 2004
    Applicant: Rambus Inc.
    Inventors: Belgacem Haba, Richard E. Perego, David Nguyen, Billy W. Garrett, Ely Tsern, Craig E. Hampel, Wai-Yeung Yip
  • Patent number: 6504448
    Abstract: A method of tuning transmission line impedance includes the step of determining a desired impedance for a transmission line. A capacitive stub is periodically added to the transmission line. A physical quantity to be removed from each of the capacitive stubs to achieve the desired impedance is identified. The identified physical quantity is then removed to establish the desired transmission line impedance. A method of forming an impedance bridge includes the step of affixing a set of capacitive stubs to a bridging transmission line that has a first end and a second end. The vertical height of the set of capacitive stubs is tapered from the first end to the second end to form an increasingly high impedance between the first end and the second end.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: January 7, 2003
    Assignee: Rambus Inc.
    Inventor: Wai-Yeung Yip
  • Publication number: 20010053069
    Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
    Type: Application
    Filed: April 20, 2001
    Publication date: December 20, 2001
    Applicant: Rambus Inc.
    Inventors: Belgacem Haba, Richard E. Perego, David Nguyen, Billy W. Garrett, Ely Tsern, Craig E. Hampel, Wai-Yeung Yip
  • Patent number: 6215373
    Abstract: A system and method are presented for stabilizing the electrical impedance of a structure (e.g., an electrical interconnecting apparatus) including a pair of parallel planar conductors separated by a dielectric layer. The structure may be, for example, a PCB, a component of a semiconductor device package, or formed upon a surface of an integrated circuit substrate. An electrical resistance connected between the planar conductors about a periphery of the structure serves to stabilize the electrical impedance of the structure, thereby reducing an amount of electromagnetic energy radiated from the structure. The electrical resistance may be multiple discrete electrical resistances dispersed about the periphery of the structure, and the structure need not be rectangular. For example, a portion of the periphery of the structure may define a curve. A general method for stabilizing the electrical impedance of the structure includes selecting a spacing distance.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: April 10, 2001
    Assignee: Sun Microsystems, Inc.
    Inventors: Istvan Novak, Wai-Yeung Yip
  • Patent number: 5694344
    Abstract: A method of electrically modeling a semiconductor package is provided. The method reduces computation time for mutual inductance calculations between interconnect lines of the semiconductor package. Only interconnect within a predetermined distance of an interconnect line being modeled is calculated for mutual inductance. The predetermined distance is selected such that any interconnect line greater than the predetermined distance away from the interconnect line being modeled produces a negligible or small mutual inductance. This greatly reduces the number of calculations for semiconductor packages having a large number of interconnect lines. Each interconnect line modeled is broken into segments for calculating mutual inductance. An algorithm is used that calculates the mutual inductance between a pair of arbitrarily oriented straight line metal segments.
    Type: Grant
    Filed: June 15, 1995
    Date of Patent: December 2, 1997
    Assignee: Motorola, Inc.
    Inventors: Wai-Yeung Yip, Arijit Chandra
  • Patent number: 5465217
    Abstract: A method for automated artwork building which comprises determining a desired die pad pitch, assigning inner lead bonding positions for each lead based on the average die pitch. The desired outer lead bonding position is then determined for each lead. The allowable range of fan in and fan out angles for each lead is computed according to design and manufacturing constraints. An electrical cost function is formulated based on signal lead crosstalk and ground lead simultaneous switching noise. Each lead is then routed. The routing is repeated for each lead for each allowable combination of fan in and fan out angles. Finally the optimal routing is selected based on electrical characteristics.
    Type: Grant
    Filed: August 16, 1993
    Date of Patent: November 7, 1995
    Assignee: Motorola, Inc.
    Inventors: Wai-Yeung Yip, Arijit Chandra, Chi-Taou Tsai
  • Patent number: 5243547
    Abstract: A plurality of conductors (10, 11, 12, 15) are formed into sections (13, 14, 16, 17, 18, 19) having uniform cross-sectional area. Per unit electrical parameters are developed for each section (13, 14, 16, 17, 18, 19). A conductor of the plurality of conductors (10, 11, 12, 15) is partitioned into a number of equal length segments. All other conductors are partitioned into the same number of segments. For each segment, a lumped element model (24, 26, 28, 29) is developed. The model (24, 26, 28, 29) includes a capacitor (33), an inductor (32), a plurality of mutual inductors (36, 38, 31), and a plurality of mutual capacitors (37, 39, 40). Each model (24, 26, 28, 29) of a conductor (10, 11, 12, 15) is serially connected to provide an equivalent circuit (23, 27) of each conductor (10, 11, 12, 15). The circuits (23, 27) are simulated to determine the amount of signal coupling. The conductors (10, 11, 12, 15) are then modified to limit the signal coupling to desired values, and the procedure is repeated.
    Type: Grant
    Filed: April 1, 1992
    Date of Patent: September 7, 1993
    Assignee: Motorola, Inc.
    Inventors: Chi-Taou Tsai, Wai-Yeung Yip