Patents by Inventor Wai-Yi Lien
Wai-Yi Lien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961892Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: June 10, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11942548Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.Type: GrantFiled: May 18, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Chih-Hao Wang, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11929417Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: June 30, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Publication number: 20230395687Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: ApplicationFiled: July 27, 2023Publication date: December 7, 2023Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11777009Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: March 14, 2022Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11769690Abstract: A device includes a substrate, a first metal feature over the substrate, first and second spacers, a first dielectric layer, and a second metal feature. The first and second spacers are on opposite sidewalls of the conductive feature, respectively. The first dielectric layer is in contact with the first spacer, in which a top surface of the protection layer is higher than a top surface of the first spacer. The second metal feature is electrically connected to the first metal structure and in contact with a top surface and a sidewall of the protection layer.Type: GrantFiled: September 1, 2021Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Chuan You, Chia-Hao Chang, Wai-Yi Lien, Yu-Ming Lin
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Publication number: 20220367268Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, a source/drain contact, a conductive structure, an interlayer dielectric (ILD) layer, an etch stop layer, and a dielectric liner. The semiconductor substrate has a channel region and a source/drain region. The gate electrode is over the channel region. The source/drain contact is over the source/drain region. The conductive structure is over a top surface of the source/drain contact. The ILD layer surrounds the conductive structure and over the gate electrode. The etch stop layer is over the conductive structure and the ILD layer. The etch stop layer comprises a material different from that of the ILD layer. A dielectric liner at a sidewall the conductive structure. The dielectric liner extends from the top surface of the source/drain contact to a bottom surface of the etch stop layer.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao CHANG, Jia-Chuan YOU, Yu-Ming LIN, Chih-Hao WANG, Wai-Yi LIEN
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Publication number: 20220328644Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: ApplicationFiled: June 30, 2022Publication date: October 13, 2022Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Publication number: 20220302277Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: ApplicationFiled: June 10, 2022Publication date: September 22, 2022Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Publication number: 20220293459Abstract: A method includes forming a gate stack over a substrate and a gate spacer on a sidewall of the gate stack; forming a source/drain region in the substrate and adjacent to the gate spacer; forming a first interlayer dielectric layer over the source/drain region; forming a protective layer over the gate stack and in contact with a top surface of the gate spacer; removing the first interlayer dielectric layer after forming the protective layer; forming an etch stop layer over the protective layer; forming a second interlayer dielectric layer over the etch stop layer; etching the second interlayer dielectric layer and the etch stop layer to form an opening that exposes a top surface of the protective layer; and forming a contact plug in the opening.Type: ApplicationFiled: June 2, 2022Publication date: September 15, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Wai-Yi LIEN, Yu-Ming LIN
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Patent number: 11437513Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.Type: GrantFiled: December 20, 2019Date of Patent: September 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Chih-Hao Wang, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11404315Abstract: A method of forming a semiconductor device includes forming an ILD structure over a source/drain region, forming a source/drain contact in the ILD structure and over the source/drain region, removing a portion of the source/drain contact such that a hole is formed in the ILD structure and over a remaining portion of the source/drain contact, forming a hole liner lining a sidewall of the hole after removing the portion of the source/drain contact, and forming a conductive structure in the hole.Type: GrantFiled: May 11, 2020Date of Patent: August 2, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao Chang, Jia-Chuan You, Yu-Ming Lin, Chih-Hao Wang, Wai-Yi Lien
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Publication number: 20220208983Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: ApplicationFiled: March 14, 2022Publication date: June 30, 2022Inventors: Carlos H. Diaz, Chung-Wei Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11355387Abstract: A method includes forming a dummy gate stack over a substrate; forming a gate spacer on a sidewall of the dummy gate stack; after forming the gate spacer, forming a source/drain region in the substrate and adjacent to the gate spacer; forming a first interlayer dielectric layer over the source/drain region and adjacent to the gate spacer; replacing the dummy gate stack with a metal gate stack; forming a protective layer over the metal gate stack and the gate spacer; after forming the protective layer, removing the first interlayer dielectric layer to expose a sidewall of the gate spacer and a sidewall of the protective layer; and forming a bottom conductive feature over the source/drain region.Type: GrantFiled: December 30, 2019Date of Patent: June 7, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Chuan You, Chia-Hao Chang, Wai-Yi Lien, Yu-Ming Lin
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Patent number: 11276763Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: November 13, 2019Date of Patent: March 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11239340Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.Type: GrantFiled: June 8, 2020Date of Patent: February 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
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Publication number: 20210398845Abstract: A device includes a substrate, a first metal feature over the substrate, first and second spacers, a first dielectric layer, and a second metal feature. The first and second spacers are on opposite sidewalls of the conductive feature, respectively. The first dielectric layer is in contact with the first spacer, in which a top surface of the protection layer is higher than a top surface of the first spacer. The second metal feature is electrically connected to the first metal structure and in contact with a top surface and a sidewall of the protection layer.Type: ApplicationFiled: September 1, 2021Publication date: December 23, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Wai-Yi LIEN, Yu-Ming LIN
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Publication number: 20210273100Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.Type: ApplicationFiled: May 18, 2021Publication date: September 2, 2021Inventors: Kuo-Cheng CHING, Ching-Wei TSAI, Carlos H. DIAZ, Chih-Hao WANG, Wai-Yi LIEN, Ying-Keung LEUNG
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Patent number: 11088250Abstract: A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure and a first spacer layer formed on the first gate structure. The FinFET device structure includes a first insulation layer formed over the fin structure, and the first insulating layer is adjacent to and separated from the first spacer layer. The FinFET device structure includes a conductive plug formed over the first gate structure, and the conductive plug is formed over the first spacer layer and the first insulation layer.Type: GrantFiled: December 17, 2018Date of Patent: August 10, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Chuan You, Chia-Hao Chang, Wai-Yi Lien, Yu-Ming Lin, Chih-Hao Wang
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Patent number: 11043579Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor fin on a substrate. A dummy gate structure is formed crossing the semiconductor fin. The dummy gate structure is replaced with a metal gate structure. An epitaxial structure is formed in the semiconductor fin after replacing the dummy gate structure with the metal gate structure.Type: GrantFiled: July 20, 2020Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hao Wang, Wai-Yi Lien, Gwan-Sin Chang, Yu-Ming Lin, Ching Hsueh, Jia-Chuan You, Chia-Hao Chang