Patents by Inventor Waichiro Fujieda
Waichiro Fujieda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8254193Abstract: There is provided a semiconductor memory device including: plural memory cells; a selection signal outputting section; a first precharging section that precharges a potential of a data line that outputs, to an exterior, a signal of a level corresponding to data stored in the memory cell; and a bit line selecting section that has, per bit line, a bit line selecting section that comprises (1) a second precharging section, (2) a potential lowering section, and (3) a third precharging section connected to the bit line selection line and the bit line between the second precharging section and a connection point at which the potential lowering section is connected to the bit line, and when the non-selection signal is inputted, the third precharging section precharges the bit line between the second precharging section and the connection point at which the potential lowering section is connected to the bit line.Type: GrantFiled: October 19, 2010Date of Patent: August 28, 2012Assignee: Lapis Semiconductor Co., Ltd.Inventor: Waichiro Fujieda
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Publication number: 20110090752Abstract: There is provided a semiconductor memory device including: plural memory cells; a selection signal outputting section; a first precharging section that precharges a potential of a data line that outputs, to an exterior, a signal of a level corresponding to data stored in the memory cell; and a bit line selecting section that has, per bit line, a bit line selecting section that comprises (1) a second precharging section, (2) a potential lowering section, and (3) a third precharging section connected to the bit line selection line and the bit line between the second precharging section and a connection point at which the potential lowering section is connected to the bit line, and when the non-selection signal is inputted, the third precharging section precharges the bit line between the second precharging section and the connection point at which the potential lowering section is connected to the bit line.Type: ApplicationFiled: October 19, 2010Publication date: April 21, 2011Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Waichiro Fujieda
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Patent number: 7592797Abstract: A plurality of switch circuits are disposed so as to correspond to a plurality of circuit blocks, respectively. Each of the plurality of switch circuits is connected between a power supply terminal of a corresponding circuit block and a power supply line. A setting circuit is disposed to set each of the plurality of switch circuits to be in a valid or invalid state. A switch control circuit turns on each of the plurality of switch circuits according to a first control signal for indicating an operation state of the plurality of circuit blocks when each of the plurality of switch circuits is set in a valid state by the setting circuit and turns on each of the plurality of switch circuits regardless of the first control signal when each of the plurality of switch circuits is set in an invalid state by the setting circuit.Type: GrantFiled: March 11, 2008Date of Patent: September 22, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Waichiro Fujieda
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Patent number: 7420860Abstract: First dummy memory cells connected to a first dummy signal line have the same shape and characteristics as those of a real memory cell. The first dummy memory cells are arranged to be adjacent to outermost real memory cells. A voltage setting circuit changes the voltage of the first dummy signal line from a first voltage to a second voltage in order to write test data onto the first dummy memory cell during a test mode. By writing data of a logic opposite to that of the test data onto the real memory cell adjacent to the first dummy memory cell by means of an operation control circuit, a leak failure that may occur between the first dummy memory cell and the real memory cell adjacent thereto can be checked.Type: GrantFiled: February 16, 2007Date of Patent: September 2, 2008Assignee: Fujitsu LimitedInventors: Shinichi Yamada, Waichiro Fujieda, Shinichiroh Ikemasu
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Publication number: 20080169804Abstract: A plurality of switch circuits are disposed so as to correspond to a plurality of circuit blocks, respectively. Each of the plurality of switch circuits is connected between a power supply terminal of a corresponding circuit block and a power supply line. A setting circuit is disposed to set each of the plurality of switch circuits to be in a valid or invalid state. A switch control circuit turns on each of the plurality of switch circuits according to a first control signal for indicating an operation state of the plurality of circuit blocks when each of the plurality of switch circuits is set in a valid state by the setting circuit and turns on each of the plurality of switch circuits regardless of the first control signal when each of the plurality of switch circuits is set in an invalid state by the setting circuit.Type: ApplicationFiled: March 11, 2008Publication date: July 17, 2008Applicant: FUJITSU LIMITEDInventor: Waichiro FUJIEDA
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Patent number: 7358718Abstract: A plurality of switch circuits are disposed so as to correspond to a plurality of circuit blocks, respectively. Each of the plurality of switch circuits is connected between a power supply terminal of a corresponding circuit block and a power supply line. A setting circuit is disposed to set each of the plurality of switch circuits to be in a valid or invalid state. A switch control circuit turns on each of the plurality of switch circuits according to a first control signal for indicating an operation state of the plurality of circuit blocks when each of the plurality of switch circuits is set in a valid state by the setting circuit and turns on each of the plurality of switch circuits regardless of the first control signal when each of the plurality of switch circuits is set in an invalid state by the setting circuit.Type: GrantFiled: May 17, 2006Date of Patent: April 15, 2008Assignee: Fujitsu LimitedInventor: Waichiro Fujieda
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Publication number: 20070205755Abstract: A plurality of switch circuits are disposed so as to correspond to a plurality of circuit blocks, respectively. Each of the plurality of switch circuits is connected between a power supply terminal of a corresponding circuit block and a power supply line. A setting circuit is disposed to set each of the plurality of switch circuits to be in a valid or invalid state. A switch control circuit turns on each of the plurality of switch circuits according to a first control signal for indicating an operation state of the plurality of circuit blocks when each of the plurality of switch circuits is set in a valid state by the setting circuit and turns on each of the plurality of switch circuits regardless of the first control signal when each of the plurality of switch circuits is set in an invalid state by the setting circuit.Type: ApplicationFiled: May 17, 2006Publication date: September 6, 2007Inventor: Waichiro Fujieda
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Publication number: 20070147146Abstract: First dummy memory cells connected to a first dummy signal line have the same shape and characteristics as those of a real memory cell. The first dummy memory cells are arranged to be adjacent to outermost real memory cells. A voltage setting circuit changes the voltage of the first dummy signal line from a first voltage to a second voltage in order to write test data onto the first dummy memory cell during a test mode. By writing data of a logic opposite to that of the test data onto the real memory cell adjacent to the first dummy memory cell by means of an operation control circuit, a leak failure that may occur between the first dummy memory cell and the real memory cell adjacent thereto can be checked.Type: ApplicationFiled: February 16, 2007Publication date: June 28, 2007Inventors: Shinichi Yamada, Waichiro Fujieda, Shinichiroh Ikemasu
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Patent number: 7184333Abstract: First dummy memory cells connected to a first dummy signal line have the same shape and characteristics as those of a real memory cell. The first dummy memory cells are arranged to be adjacent to outermost real memory cells. A voltage setting circuit changes the voltage of the first dummy signal line from a first voltage to a second voltage in order to write test data onto the first dummy memory cell during a test mode. By writing data of a logic opposite to that of the test data onto the real memory cell adjacent to the first dummy memory cell by means of an operation control circuit, a leak failure that may occur between the first dummy memory cell and the real memory cell adjacent thereto can be checked.Type: GrantFiled: December 3, 2004Date of Patent: February 27, 2007Assignee: Fujitsu LimitedInventors: Shinichi Yamada, Waichiro Fujieda, Shinichiroh Ikemasu
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Patent number: 7032142Abstract: A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.Type: GrantFiled: October 17, 2002Date of Patent: April 18, 2006Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Waichiro Fujieda, Kota Hara, Toru Koga, Katsuhiro Mori
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Publication number: 20050278592Abstract: First dummy memory cells connected to a first dummy signal line have the same shape and characteristics as those of a real memory cell. The first dummy memory cells are arranged to be adjacent to outermost real memory cells. A voltage setting circuit changes the voltage of the first dummy signal line from a first voltage to a second voltage in order to write test data onto the first dummy memory cell during a test mode. By writing data of a logic opposite to that of the test data onto the real memory cell adjacent to the first dummy memory cell by means of an operation control circuit, a leak failure that may occur between the first dummy memory cell and the real memory cell adjacent thereto can be checked.Type: ApplicationFiled: December 3, 2004Publication date: December 15, 2005Inventors: Shinichi Yamada, Waichiro Fujieda, Shinichiroh Ikemasu
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Patent number: 6754126Abstract: A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.Type: GrantFiled: March 27, 2002Date of Patent: June 22, 2004Assignee: Fujitsu LimitedInventors: Shusaku Yamaguchi, Toshiya Uchida, Yoshimasa Yagishita, Yoshihide Bando, Masahiro Yada, Masaki Okuda, Hiroyuki Kobayashi, Kota Hara, Shinya Fujioka, Waichiro Fujieda
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Patent number: 6731553Abstract: A multi-bit output configuration memory circuit comprises: a memory core having a normal cell array and a redundant cell array, which have a plurality of memory cells; N output terminals which respectively output N-bit output read out from the memory core; an output circuit provided between the output terminals and the memory core, which detects whether each L-bit output of the N-bit output (N=L×M) read out from said memory core matches or not and outputs a compressed output which becomes the output data in the event of a match while becomes a third state in the event of a non-match, to a first output terminal of the N output terminals. Responding to each of a plurality of test commands or the test control signals of the external terminals, the compressed output of the M groups of L-bit output is outputted in time shared.Type: GrantFiled: October 15, 2002Date of Patent: May 4, 2004Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Waichiro Fujieda, Kota Hara
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Publication number: 20030106010Abstract: A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.Type: ApplicationFiled: October 17, 2002Publication date: June 5, 2003Applicant: FUJITSU LIMITEDInventors: Shinya Fujioka, Waichiro Fujieda, Kota Hara, Toru Koga, Katsuhiro Mori
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Publication number: 20030099143Abstract: A multi-bit output configuration memory circuit comprises: a memory core having a normal cell array and a redundant cell array, which have a plurality of memory cells; N output terminals which respectively output N-bit output read out from the memory core; an output circuit provided between the output terminals and the memory core, which detects whether each L-bit output of the N-bit output (N=L×M) read out from said memory core matches or not and outputs a compressed output which becomes the output data in the event of a match while becomes a third state in the event of a non-match, to a first output terminal of the N output terminals. Responding to each of a plurality of test commands or the test control signals of the external terminals, the compressed output of the M groups of L-bit output is outputted in time shared.Type: ApplicationFiled: October 15, 2002Publication date: May 29, 2003Applicant: FUJITSU LIMITEDInventors: Shinya Fujioka, Waichiro Fujieda, Kota Hara
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Patent number: 6545924Abstract: A semiconductor memory device having a self-refresh function includes a detection circuit detecting a change of an output enable signal and generating a state transition detection signal, and a decision circuit comparing the state transition detection signal and a refresh request signal internally generated and generating a signal that indicates a corresponding circuit operation.Type: GrantFiled: August 15, 2001Date of Patent: April 8, 2003Assignee: Fujitsu LimitedInventors: Waichiro Fujieda, Shinya Fujioka
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Publication number: 20030026161Abstract: A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.Type: ApplicationFiled: March 27, 2002Publication date: February 6, 2003Applicant: FUJITSU LIMITEDInventors: Shusaku Yamaguchi, Toshiya Uchida, Yoshimasa Yagishita, Yoshihide Bando, Masahiro Yada, Masaki Okuda, Hiroyuki Kobayashi, Kota Hara, Shinya Fujioka, Waichiro Fujieda
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Patent number: 6477093Abstract: An address signal is transmited to a decoder before the activation of a control signal operating a memory cell. Here, the decoder is inactivated. Subsequently, after the activation of the control signal, the reception of a new address signal is inhibited, and the decoder is activated at the same time. Therefore, the decoder starts operating at an earlier timing of the operating cycle, outputting a decoding signal. This means reduction in access time. Moreover, the reception of a new address signal is inhibited after the activation of the control signal. This prevents the decoder from decoding incorrect address signals ascribable to noises and the like, thereby avoiding malfunctions.Type: GrantFiled: July 11, 2001Date of Patent: November 5, 2002Assignee: Fujitsu LimitedInventors: Yoshiaki Okuyama, Shinya Fujioka, Waichiro Fujieda
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Patent number: 6427197Abstract: The present invention is a memory circuit for writing prescribed numbers of bits of write data, determined according to the burst length, in response to write command, comprising: a first stage for inputting, and then holding, row addresses and column addresses simultaneously with the write command; a second stage having a memory core connected to the first stage via a pipeline switch, wherein the row addresses and column addresses are decoded, and word line and sense amps are activated; a third stage for inputting the write data serially and sending the write data to the memory core in parallel; and a serial data detection circuit for generating write-pipeline control signal for making the pipeline switch conduct, after the prescribed number of bits of write data has been inputted. According to the present invention, in an FCRAM exhibiting a pipeline structure, the memory core in the second stage can be activated after safely fetching the write data in the burst length.Type: GrantFiled: September 13, 1999Date of Patent: July 30, 2002Assignee: Fujitsu LimitedInventors: Yasuharu Sato, Tadao Aikawa, Shinya Fujioka, Waichiro Fujieda, Hitoshi Ikeda, Hiroyuki Kobayashi
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Patent number: 6377100Abstract: A semiconductor device, comprising a stabilized timing circuit for regulating the phase of each of first and second clocks complementary with each other input from an external source and generating each of first and second internal clocks delayed by a predetermined phase, is disclosed. The stabilized timing circuit includes a clock input circuit unit for receiving the first and second clocks complementary with each other, and a dummy input circuit unit for receiving a first feedback clock and a second feedback clock complementary with each other and having the delay time equivalent to the delay time of the first and second clocks in the clock input circuit unit.Type: GrantFiled: June 28, 2000Date of Patent: April 23, 2002Assignee: Fujitsu LimitedInventor: Waichiro Fujieda