Patents by Inventor Wajdi K. Feghali

Wajdi K. Feghali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Filter for network intrusion and virus detection
    Patent number: 9270698
    Abstract: Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Christopher F. Clark, Gilbert M. Wolrich, Wajdi K. Feghali
  • Instructions to perform JH cryptographic hashing
    Patent number: 9251374
    Abstract: A method is described. The method includes executing one or more JH_SBOX_L instruction to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_Permute instruction to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 2, 2016
    Assignee: Intel Corporation
    Inventors: Kirk S. Yap, Gilbert M. Wolrich, Vinodh Gopal, James D. Guilford, Erdinc Ozturk, Sean M. Gulley, Wajdi K. Feghali, Martin G. Dixon
  • SIMD integer multiply-accumulate instruction for multi-precision arithmetic
    Patent number: 9235414
    Abstract: A multiply-and-accumulate (MAC) instruction allows efficient execution of unsigned integer multiplications. The MAC instruction indicates a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination. The first vector register stores a first factor, and the second vector register stores a partial sum. The MAC instruction is executed to multiply the first factor with an implicit second factor to generate a product, and to add the partial sum to the product to generate a result. The first factor, the implicit second factor and the partial sum have a same data width and the product has twice the data width. The most significant half of the result is stored in the third vector register, and the least significant half of the result is stored in the second vector register.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: January 12, 2016
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Gilbert M. Wolrich, Erdinc Ozturk, James D. Guilford, Kirk S. Yap, Sean M. Gulley, Wajdi K. Feghali, Martin G. Dixon
  • Architecture and instruction set for implementing advanced encryption standard (AES)
    Patent number: 9230120
    Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: January 5, 2016
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal
  • Bitstream processing using coalesced buffers and delayed matching and enhanced memory writes
    Patent number: 9203887
    Abstract: Methods and apparatus for processing bitstreams and byte streams. According to one aspect, bitstream data is compressed using coalesced string match tokens with delayed matching. A matcher is employed to perform search string match operations using a shortened maximum string length search criteria, resulting in generation of a token stream having <len, distance> data and literal data. A distance match operation is performed on sequentially adjacent tokens to determine if they contain the same distance data. If they do, the len values of the tokens are added through use of a coalesce buffer. Upon detection of a distance non-match, a final coalesced length of a matching string is calculated and output along with the prior matching distance as a coalesced token.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: December 1, 2015
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Jim D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Deniz Karakoyunlu, Erdinc Ozturk, Martin Dixon, Kahraman Akdemir
  • METHOD AND APPARATUS FOR EFFICIENTLY EXECUTING HASH OPERATIONS
    Publication number: 20150280917
    Abstract: An apparatus and method are described for executing hash functions on a processor.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: GILBERT M. WOLRICH, VINODH GOPAL, KIRK S. YAP, WAJDI K. FEGHALI
  • Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic
    Patent number: 9141469
    Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Sivakumar Radhakrishnan, Mark A. Schmisseur, Sin S. Tan, Kenneth C. Haren, Thomas C. Brown, Pankaj Kumar, Vinodh Gopal, Wajdi K. Feghali
  • Instructions processors, methods, and systems to process BLAKE secure hashing algorithm
    Patent number: 9100184
    Abstract: A method of an aspect includes receiving an instruction indicating a first source having at least one set of four state matrix data elements, which represent a complete set of four inputs to a G function of a cryptographic hashing algorithm. The algorithm uses a sixteen data element state matrix, and alternates between updating data elements in columns and diagonals. The instruction also indicates a second source having data elements that represent message and constant data. In response to the instruction, a result is stored in a destination indicated by the instruction. The result includes updated state matrix data elements including at least one set of four updated state matrix data elements. Each of the four updated state matrix data elements represents a corresponding one of the four state matrix data elements of the first source, which has been updated by the G function.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 4, 2015
    Assignee: Intel Corporation
    Inventors: Gilbert M. Wolrich, Kirk S. Yap, James D. Guilford, Vinodh Gopal, Erdinc Ozturk, Sean M. Gulley, Wajdi K. Feghali, Martin G. Dixon
  • Efficient multiplication, exponentiation and modular reduction implementations
    Patent number: 9092645
    Abstract: In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: July 28, 2015
    Assignee: Intel Corporation
    Inventors: Erdinc Ozturk, Vinodh Gopal, Gilbert M. Wolrich, Wajdi K. Feghali, James D. Guilford, Deniz Karakoyunlu, Martin G. Dixon, Kahraman D. Akdemir
  • SM3 HASH FUNCTION MESSAGE EXPANSION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    Publication number: 20150186139
    Abstract: A processor includes a decode unit to receive an instruction to indicate a first source packed data operand and a second source packed data operand. The source operands each to include elements. The data elements to include information selected from messages and logical combinations of messages that is sufficient to evaluate: P1(Wj?16 XOR Wj?9 XOR(Wj?3<<<15))XOR(Wj?13<<<7)XOR Wj?6 P1 is a permutation function, P1(X)=X XOR (X<<<15) XOR (X<<<23). Wj?16, Wj?9, Wj?3, Wj?13, and Wj?6 are messages associated with a compression function of an SM3 hash function. XOR is an exclusive OR operation. <<< is a rotate operation. An execution unit coupled with the decode unit that is operable, in response to the instruction, to store a result packed data in a destination storage location. The result packed data to include a Wj message to be input to a round j of the compression function.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Inventors: Gilbert M. Wolrich, Vinodh Gopal, Kirk S. Yap, Wajdi K. Feghali, Sean Gulley
  • SMS4 ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    Publication number: 20150186138
    Abstract: A processor of an aspect includes a plurality of packed data registers and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SMS4 rounds. The one or more source operands are also to have a 32-bit value. An execution unit is coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store a 32-bit result of a current SMS4 round in a destination storage location that is to be indicated by the instruction.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Inventors: Gilbert M. Wolrich, Vinodh Gopal, Kirk S. Yap, Wajdi K. Feghali
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20150169474
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 18, 2015
    Applicant: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • USING A MEMORY ADDRESS TO FORM A TWEAK KEY TO USE TO ENCRYPT AND DECRYPT DATA
    Publication number: 20150169472
    Abstract: Provided are a memory system, memory controller, and method for using a memory address to form a tweak key to use to encrypt and decrypt data. A base tweak co is generated as a function of an address of a block of data in the memory storage. For each sub-block of the block, performing: processing the base tweak to determine a sub-block tweak; combining the sub-block tweak with the sub-block to produce a modified sub-block; and performing an encryption operation comprising one of encryption or decryption on the modified sub-block to produce sub-block output comprising one of encrypted data and unencrypted data for the sub-block.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 18, 2015
    Inventors: Kirk S. YAP, Gilbert M. WOLRICH, Vinodh GOPAL, Wajdi K. FEGHALI
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20150169473
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 18, 2015
    Applicant: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Method and apparatus for efficient programmable cyclic redundancy check (CRC)
    Patent number: 9052985
    Abstract: A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data decreases area used to perform the reduction while maintaining the same delay through the plurality of stages of the reduction logic. A hybrid mix of Karatsuba algorithm, classical multiplications and serial division in various stages in the CRC reduction circuit results in about a twenty percent reduction in area on the average with no decrease in critical path delay.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: June 9, 2015
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Erdinc Ozturk, Gilbert M. Wolrich, Wajdi K. Feghali
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20150154122
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 4, 2015
    Applicant: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20150104007
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 16, 2015
    Applicant: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20150104010
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 16, 2015
    Applicant: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20150104008
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 16, 2015
    Applicant: INTEL CORPORATION
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20150104009
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 16, 2015
    Applicant: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis