Patents by Inventor Waley Li

Waley Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8179187
    Abstract: A method for passive cancellation of substrate noise for a buck converter uses an on-chip capacitor to reduce the substrate noise. The capacitor achieves a close-magnitude noise with opposite phase for better noise cancellation effect in the substrate. The capacitor can be realized as a MOS capacitor, NMOS isolation ring n-well capacitor, n-well junction capacitor, isolated p-well junction capacitor, etc. The capacitor is easy to implement. Further, bond wire parasitic inductance in the buck converter is used to reduce substrate noise.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: May 15, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongwei Zhao, Jian Yang, Iven Zheng, Tommy Mao, Waley Li
  • Patent number: 7940092
    Abstract: An H bridge circuit includes a gate driver circuit coupled to a gate of an NMOS device. The output of the gate driver circuit is at a voltage from 0.1V to 0.4V during a dead time of the H bridge circuit. The gate voltage of the NMOS device is biased at 0.1˜0.4V to overcome the problems of minority carrier injection and power dissipation as compared with VG=0 in a conventional H bridge circuit.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: May 10, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Iven Zheng, Waley Li, Linpeng Wei, Hongwei Zhao, Weiying Li
  • Publication number: 20100102875
    Abstract: A method for passive cancellation of substrate noise for a buck converter uses an on-chip capacitor to reduce the substrate noise. The capacitor achieves a close-magnitude noise with opposite phase for better noise cancellation effect in the substrate. The capacitor can be realized as a MOS capacitor, NMOS isolation ring n-well capacitor, n-well junction capacitor, isolated p-well junction capacitor, etc. The capacitor is easy to implement. Further, bond wire parasitic inductance in the buck converter is used to reduce substrate noise.
    Type: Application
    Filed: October 13, 2009
    Publication date: April 29, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Hongwei Zhao, Jian Yang, Iven Zheng, Tommy Mao, Waley Li
  • Publication number: 20100079194
    Abstract: An H bridge circuit includes a gate driver circuit coupled to a gate of an NMOS device. The output of the gate driver circuit is at a voltage from 0.1V to 0.4V during a dead time of the H bridge circuit. The gate voltage of the NMOS device is biased at 0.1˜0.4V to overcome the problems of minority carrier injection and power dissipation as compared with VG=0 in a conventional H bridge circuit.
    Type: Application
    Filed: September 8, 2009
    Publication date: April 1, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Iven ZHENG, Waley LI, Linpeng WEI, Hongwei ZHAO, Weiying LI