Patents by Inventor Walter Anthony Wohlmuth

Walter Anthony Wohlmuth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Combined micro-electro-mechanical systems device and integrated circuit on a silicon-on-insulator wafer
    Patent number: 7863071
    Abstract: The present invention includes a fabrication method to construct a combined MEMS device and IC on a silicon-on-insulator (SOI) wafer (MEMS-IC) using standard foundry IC processing techniques. The invention also includes the resulting MEMS-IC. Deposition layers are added to the SOI wafer and etched away to form interconnects for electronic components for the IC. In one embodiment of the present invention, standard foundry IC processing etching techniques may be used to etch away parts of the insulating layer and device layer of the SOI wafer to create fine gaps and other detailed mechanical features of the MEMS device. Finely detailed etching patterns may be added by using imprint lithography instead of using contact or optical lithography.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: January 4, 2011
    Assignee: RF Micro Devices, Inc.
    Inventors: Tony Ivanov, Julio Costa, Jonathan Hale Hammond, Walter Anthony Wohlmuth
  • Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same
    Patent number: 7655546
    Abstract: A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure. The multi-layer structure includes a channel layer overlaid by a barrier layer overlaid by an ohmic contact layer. Source and drain contacts of the D-mode and E-mode FETs are coupled to the ohmic contact layer. A gate contact of the D-mode and E-mode FETs is coupled to the barrier layer. An amorphized region is provided beneath the E-mode gate contact within the barrier layer. The amorphized region forms a buried E-mode Schottky contact with the barrier layer. An alternative embodiment couples the gate contact of the D-mode transistor to a first layer that overlies the barrier layer, and provides a similar D-mode amorphized region within the first layer.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: February 2, 2010
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: Walter Anthony Wohlmuth
  • Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same
    Patent number: 7449728
    Abstract: A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure. The multi-layer structure includes a channel layer overlaid by a barrier layer overlaid by an ohmic contact layer. Source and drain contacts of the D-mode and E-mode FETs are coupled to the ohmic contact layer. A gate contact of the D-mode and E-mode FETs is coupled to the barrier layer. An amorphized region is provided beneath the E-mode gate contact within the barrier layer. The amorphized region forms a buried E-mode Schottky contact with the barrier layer. An alternative embodiment couples the gate contact of the D-mode transistor to a first layer that overlies the barrier layer, and provides a similar D-mode amorphized region within the first layer.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: November 11, 2008
    Assignee: Tri Quint Semiconductor, Inc.
    Inventor: Walter Anthony Wohlmuth