Patents by Inventor Walter C. Dietrich, Jr.

Walter C. Dietrich, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6282318
    Abstract: A method for combining pattern matching and optimization. The method includes the steps of reading the data elements and corresponding attributes for each of the two data files; performing pattern matching on the elements and the corresponding attributes of each of the two files read in this step; performing optimization on the results for finding a best total matching of the elements of the two files; and, outputting a file selected from the group consisting of the matches produced by step 3, and a file containing the elements that are not matched.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: August 28, 2001
    Assignee: International Business Machines Corporation
    Inventors: Brenda Lynn Dietrich, Walter C. Dietrich, Jr.
  • Patent number: 5787283
    Abstract: A tool including a framework suitable for manufacturing logistics decision support. The tool comprises means for providing an object-oriented technology framework, the framework comprising: means for defining objects representing manufacturing logistics problems; means for transforming a subject of the above objects into representations commonly used in a mathematical solver, wherein the representations in the solver have predefined relationships based on their properties; and, means responsive to selective changes in the objects for modifying the behavior of the framework for developing anew manufacturing logistics decision support application.
    Type: Grant
    Filed: October 27, 1995
    Date of Patent: July 28, 1998
    Assignee: International Business Machines Corporation
    Inventors: Goodwin R. Chin, Walter C. Dietrich, Jr., Thomas Robert Ervolina, John Peter Fasano, Elizabeth Jodi Poole, Jung-Mu Tang
  • Patent number: 5787001
    Abstract: A method for invoking an arbitrary sorting technique in a type-safe way. In one aspect, the method comprises the steps of providing a hierarchical schedule class comprising a schedule float subclass and a sorting schedule float subclass, subsumed by the schedule float subclass. The sorting schedule float subclass, in turn, comprises a schedule attribute class; a filter class; and a pair compare class. The method further includes using the hierarchical schedule class with each of an independent group consisting of a schedule attribute strategy, a filter strategy and a pair compare class strategy.
    Type: Grant
    Filed: July 20, 1995
    Date of Patent: July 28, 1998
    Assignee: IBM Corporation
    Inventors: Walter C. Dietrich, Jr., Thomas Robert Ervolina, John Peter Fasano, Jung-Mu Tang
  • Patent number: 5739824
    Abstract: The invention discloses an apparatus for conveying higher dimensional tabular information to people using a lower dimensional output device. The apparatus is such that original information in the higher dimensional expression can be mapped to the lower dimensional output device, while preserving invariant a content and relationship of the original information.
    Type: Grant
    Filed: January 9, 1997
    Date of Patent: April 14, 1998
    Assignee: International Business Machines Corporation
    Inventors: Brenda Lynn Dietrich, Walter C. Dietrich, Jr., Elizabeth Jodi Poole, John Peter Fasano, Jung-Mu Tang
  • Patent number: 5457789
    Abstract: In a multiprocessor system, memory accesses by the individual processing elements are checked by a common controller. The controller includes a table of values defining valid memory locations for a task. The controller verifies the address value used by each instruction to ensure that, it is within a valid memory area for the particular task. Additional circuitry for the controller and processing elements allows finer control, of memory accessibility. The multiprocessor system may be coupled to a host computer through a buffer. Data is serially written into the buffer by the host and is read out of the buffer in parallel by the multiprocessor system. The buffer used in this system includes apparatus which calculates an error correction code from a serial data stream and passes this code, along with the data, to the multiprocessor system. The multiprocessor system includes apparatus which processes the data in parallel to handle errors occurring during transfers as indicated by the code.
    Type: Grant
    Filed: February 19, 1993
    Date of Patent: October 10, 1995
    Assignee: International Business Machines Corporation
    Inventors: Walter C. Dietrich, Jr., Mark A. Lavin, Hungwen Li, Ming-Cheng Sheng