Patents by Inventor Walter E. Mlynko

Walter E. Mlynko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6221775
    Abstract: A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: April 24, 2001
    Assignee: International Business Machines Corp.
    Inventors: Thomas G. Ference, William F. Landers, Michael J. MacDonald, Walter E. Mlynko, Mark P. Murray, Kirk D. Peterson
  • Patent number: 6147394
    Abstract: The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: November 14, 2000
    Assignee: International Business Machines Corporation
    Inventors: James A. Bruce, Steven J. Holmes, Robert K. Leidy, Walter E. Mlynko, Edward W. Sengle
  • Patent number: 5972570
    Abstract: The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: October 26, 1999
    Assignee: International Business Machines Corporation
    Inventors: James A. Bruce, Steven J. Holmes, Robert K. Leidy, Walter E. Mlynko, Edward W. Sengle
  • Patent number: 5672537
    Abstract: Polysilicon (20) in a trench (21) is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall (26) of the trench (21) closest the beam source. Specifically, when the first side wall (26) is closest the beam source and the second side wall (27) is furthest from the beam source, the polysilicon on the first side wall (26) is almost as high as the first side wall (26), while the polysilicon on the more exposed side wall (27) is considerably lower than the first side wall (26) and approximates the shadow of the first side wall (26) on the second side wall (27) relative to the beam.
    Type: Grant
    Filed: September 17, 1996
    Date of Patent: September 30, 1997
    Assignee: International Business Machines Corporation
    Inventors: Daniel A. Carl, Donald M. Kenney, Walter E. Mlynko, Son Van Nguyen
  • Patent number: 5610441
    Abstract: Polysilicon in a trench is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall of the trench closest the beam source. Specifically, when the first side wall is closest to the beam source and the second side wall is furthest from the beam source, the polysilicon on the first side wall is almost as high as the first side wall, while the polysilicon on the more exposed side wall is considerably lower than the first side wall and approximates the shadow of the first side wall on the second side wall relative to the beam. The polysilicon in the trench may be in the shape of a solid angled block approximating the shadow line from the top of side wall to the shadow line on side wall however, it is preferred that the polysilicon take the form of a conformal layer in trench prior to etching such that the polysilicon ultimately has an angled "U" shape which approximates the shadow line.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: March 11, 1997
    Assignee: International Business Machines Corporation
    Inventors: Daniel A. Carl, Donald M. Kenney, Walter E. Mlynko, Son V. Nguyen
  • Patent number: 5312717
    Abstract: A method for transferring a pattern through a photoresist layer in the fabrication of submicron semiconductor devices structures is disclosed. A photoresist is provided on a substrate and the same is imagewise exposed with a desired pattern to form exposed and unexposed patterned areas in the top surface of the photoresist. The photoresist is then baked to form cross-linked regions in the exposed pattern areas of the photoresist. Silylation is then performed to incorporate silicon into the unexposed patterned areas of the photoresist, wherein some incorporation of silicon occurs in the exposed patterned crosslinked areas of the photoresist. The patterned photoresist is subsequently etched using a high density, low pressure, anisotropic O.sub.2 plasma alone to produce residue-free images with vertical wall profiles in the photoresist. This method is particularly advantageous with RFI reactive ion etch systems.
    Type: Grant
    Filed: September 24, 1992
    Date of Patent: May 17, 1994
    Assignee: International Business Machines Corporation
    Inventors: Harbans S. Sachdev, John C. Forster, Leo L. Linehan, Scott A. MacDonald, K. Paul L. Muller, Walter E. Mlynko, Linda K. Somerville
  • Patent number: 5110409
    Abstract: Increased etching rates are obtained by plasma etching wherein the power is applied in a cyclical or oscillating mode.
    Type: Grant
    Filed: December 21, 1990
    Date of Patent: May 5, 1992
    Assignee: IBM
    Inventors: Frank D. Egitto, Walter E. Mlynko
  • Patent number: 5053104
    Abstract: A plasma etching process is disclosed wherein the substrate to be etched is first exposed to an etchant gas containing a volatile organohalide. When the etch rate is stabilized, the organohalide in the etchant gas is replaced by oxygen whereby the etch rate of the substrate is immediately increased to a substantially higher value. When the above is repeatedly done a substantially higher average etch rate is obtained.
    Type: Grant
    Filed: November 29, 1989
    Date of Patent: October 1, 1991
    Assignee: International Business Machines Corporation
    Inventors: Suryadevara V. Babu, Joseph G. Hoffarth, Allan R. Knoll, Walter E. Mlynko, John F. Rembetski, Kenneth D. Mack
  • Patent number: 4985112
    Abstract: Increased etching rates are obtained by plasma etching wherein the power is applied in a cyclical or oscillating mode.
    Type: Grant
    Filed: February 9, 1987
    Date of Patent: January 15, 1991
    Assignee: International Business Machines Corporation
    Inventors: Frank D. Egitto, Walter E. Mlynko
  • Patent number: 4853081
    Abstract: Contaminant is removed from the interior of the holes in the vicinity of preselected locations by etching in a gaseous plasma wherein the sheath voltage is controlled in order to direct ions of the plasma to contact the interior of the holes in the vicinity of the preselected locations.
    Type: Grant
    Filed: October 30, 1987
    Date of Patent: August 1, 1989
    Assignee: IBM Corporation
    Inventor: Walter E. Mlynko
  • Patent number: 4654115
    Abstract: Contaminant is removed from holes by etching in a gaseous plasma by first removing contaminant from the vicinity of the edges of the hole. Next, a mask is provided in the vicinity of the edges to prevent etching by contacting with a gaseous plasma which is different from the gaseous plasma employed in the first etching step. The holes are then etched in a gaseous plasma to remove contaminant from the interior of the holes in the vicinity of the center of the holes, whereby the mask protects the edges from being etched.
    Type: Grant
    Filed: April 8, 1986
    Date of Patent: March 31, 1987
    Assignee: International Business Machines Corporation
    Inventors: Frank D. Egitto, Francis Emmi, Walter E. Mlynko, Robin A. Susko