Abstract: Techniques and systems for monitoring cardiac arrhythmias and delivering electrical stimulation therapy using a subcutaneous implantable cardioverter defibrillator (SICD) and a leadless pacing device (LPD) are described. For example, the SICD may detect a tachyarrhythmia within a first electrical signal from a heart and determine, based on the tachyarrhythmia, to deliver anti-tachyarrhythmia shock therapy to the patient to treat the detected arrhythmia. The LPD may receive communication from the SICD requesting the LPD deliver anti-tachycardia pacing to the heart and determine, based on a second electrical signal from the heart sensed by the LPD, whether to deliver anti-tachycardia pacing (ATP) to the heart. In this manner, the SICD and LPD may communicate to coordinate ATP and/or cardioversion/defibrillation therapy. In another example, the LPD may be configured to deliver post-shock pacing after detecting delivery of anti-tachyarrhythmia shock therapy.

Abstract: A video correction system and method are disclosed that provide video correction for an input signal. The system includes a logarithmic converter that creates a logarithmic representation of the input signal. A configurable corrector/converter comprises a plurality of associated components operative to process the logarithmic representation of the input signal. The configurable corrector/converter produces an output signal having at least one desirable signal characteristic. A switch control selects a configuration for the corrector/converter. The configuration indicates at least one of the plurality of associated components that will process the logarithmic representation.

Abstract: A system and method is provided for determining a logarithm of an input value and a system and method for determining an inverse logarithm for an input value. The system and method determine an integer value relating to the logarithm and performs a linear interpolation over a range relating to the integer value. A mantissa value is produced from the linear interpolation and corrected over one or more correction stages. The inverse logarithmic system and method receive an input value comprising an integer value and a mantissa value. The mantissa value is precorrected over one or more precorrection stages. The precorrected mantissa is then combined with a value related to the integer value and multiplied by a restoration factor to produce the inverse logarithm.

Abstract: A video correction system and method are disclosed that provide video correction for an input signal. The system includes a logarithmic converter that creates a logarithmic representation of the input signal. A configurable corrector/converter comprises a plurality of associated components operative to process the logarithmic representation of the input signal. The configurable corrector/converter produces an output signal having at least one desirable signal characteristic. A switch control selects a configuration for the corrector/converter. The configuration indicates at least one of the plurality of associated components that will process the logarithmic representation.

Abstract: The invention relates to a digital low-pass filter which effects a frequency reduction by a factor which is equal to the ratio w/2 between the frequency of the input signal and the frequency of the output signal, wherein w is an odd integer. The input signal is applied to m series-arranged registers. The input signal of the first and the output signals of all the registers are multiplied by coefficients. A change-over switch precedes an input of each multiplier, the change-over switch switching the coefficients symmetrically. The switching instants are always symmetrical relative to a reference sampling instant. The filter is particularly suitable for use in video signal processing, to reduce negative influences of an analog-to-digital converter.

Abstract: An input signal comprising pulses in periodical intervals and being present as a series of digital sampling values is applied to a correlator for generating a correlator output signal which assumes an extreme value in the case of a pulse. The correlator comprises a chain of at least two cascaded delay members, the first of which receives the input signal. A pulse and pulse-free interval, respectively is associated with each delay member of the series, the delay members succeeding each other in the same manner as the pulses or pulse-free intervals occur. All but at most one delay member at the beginning or end of the chain can store just all sampling values of the associated pulse or pulse-free interval. The input signal of the first delay member and the output signals of all delay members are applied to a combination circuit which linearly combines and integrates the signals and forms the output signal of the correlator.

Abstract: In a circuit arrangement for converting an analog picture signal, which corresponds to consecutive fields, into an amplitude-discrete output signal, which, in a comparison stage, compares the picture signal to a plurality of reference values and produces an amplitude-discrete intermediate signal at an output, a significant simplification of the circuit cost and design effort is accomplished with, at the same time, an improvement in the error cancellation by the fact that the change in the positions of the values of the picture signal and the reference values relative to each other corresponds to the sum of a fraction and a first integral number of value intervals.

Abstract: A digital television receiver, having a line locked clock, includes a first digital phase locked loop which regenerates quadrature phase related subcarrier signals that are used to synchronously demodulate the chrominance signal components of composite video signals into color information signals. When nonstandard video signals (e.g., from a video tape recorder) are processed by the receiver, frequency instabilities in the line locked clock signal may cause the color information signals to be distorted. To compensate for this distortion, a second phase locked loop is synchronized to a reference signal generated by an analog oscillator. The analog reference signal is linearly added to baseband analog video signals provided by a tuner. The combined signals are digitized by an analog-to-digital converter and then filtered by parallel low-pass and band-pass filters to develop digital signals representing the video signals and the reference signal, respectively.

Abstract: A digital television receiver which uses a line-locked clock signal employs chrominance signal demodulation circuitry which produces a digital oscillatory signal that is locked in phase to the color reference burst signal component of the incoming video signals. An analog voltage controlled oscillator generates an oscillatory signal having a frequency of approximately twice the color subcarrier frequency. This signal is combined with the composite video signals and the combined signal is digitized by an analog to digital converter. The digitized oscillatory signal is separated from the combined digital signal and is used to synchronize a digital phase locked loop. The digital phase locked loop generates two quadrature phase related signals having frequencies that are one-half the frequency of the analog oscillatory signal. These two signals are used to synchronously demodulate the chrominance signal components of the incoming video signals to obtain two quadrature phase related color difference signals.

Abstract: A digital television receiver includes a first phase locked loop which develops a sampling clock signal that is locked to the horizontal line synchronizing signal components of a composite video signal. A second digital phase locked loop is clocked by the sampling clock signal and develops a digital signal that is phase locked to the color burst signal. This digital signal is used as a regenerated color subcarrier signal to synchronously demodulate the chrominance components of the composite video signals into I and Q color difference signals. To compensate for frequency instability in the regenerated subcarrier signal caused by frequency instabilities in the line-locked clock signal, a third digital phase locked loop develops an output signal which is phase locked to a reference signal generated by a crystal controlled oscillator.

Abstract: A digital television receiver includes a first phase locked loop which develops a sampling clock signal that is locked to the horizontal line synchronizing signals components of a composite video signal. A second digital phase locked loop is clocked by the sampling clock signal and develops a digital signal that is phase locked to the color burst signal. This signal is used as a regenerated color subcarrier signal to synchronously demodulate the chrominance components of the composite video signal into I and Q color difference signals. To compensate for frequency instabilities in the regenerated subcarrier signal caused by frequency instabilities in the line-locked clock signal, a third digital phase locked loop develops an oscillatory signal which is phase locked to a reference signal generated by a crystal controlled oscillator. Control signals from the third phase locked loop are applied to circuitry which develops control signal that is independent of the crystal frequency.

Abstract: A digital television receiver, having a line-locked clock, includes a partly digital, partly analog phase locked loop. This phase locked loop regenerates two quadrature phase related subcarrier signals that are used to synchronously demodulate the chrominance signal components of the composite video signals into two color informaiton signals. The phase locked loop includes an analog voltage controlled oscillator which generates a signal that is independent of any frequency instability in the line locked clock signal. An analog-to-digital converter digitizes this signal to provide one of the subcarrier signals. This subcarrier signal is applied to a read-only memory to generate the second subcarrier signal. The two color information signals are obtained by multiplying the chrominance signals by the first and second subcarrier signals.

Abstract: In a circuit arrangement for synchronization of the phase of a frequency-divided signal with an edge of finite slope of an essentially periodic synchronizing signal with an oscillator supplying a clock signal, a frequency divider which generates the frequency-divided signal and a phase detector which comprises a first comparator for coarse phase detection, a second comparator for fine phase detection and a selector circuit which derives a resulting phase signal applied to the oscillator to control the frequency of the clock signal and originating from the first comparator in the case of large phase variations and from the second comparator in the case of small phase variations, precise adjustment to the edge is nevertheless achieved in the case of an amplitude-discrete synchronizing signal with limited time resolution because of the fact that the synchronizing signal is applied to the phase detector as a sequence of amplitude-discrete values which is formed by sampling the synchronizing signal with the clock

Abstract: In a method of increasing the resolution of a digitized time-dependent signal, particularly a picture signal, which consists of a sequence of sampling values, teaches the forming at one sampling value an associated mean value with higher resolution. The associated mean value is formed from the sampling value and at least one succeeding and/or preceding sampling value. When the sampling value is replaced by the associated mean value, obliteration of rapid signal changes is eliminated; and circuit complexity is minimized by the fact that a sampling value is replaced by the associated mean value only when these two values differ from one another by no more than a preset amount. A circuit for implementing this method is also disclosed.

Abstract: In a circuit arrangement for converting a digital input signal into an analog output signal, comprising a voltage divider chain which, between its ends which are supplied by at least one reference voltage, has a plurality of taps which, under the control of the digital input signal, are connectable to an output for deriving the analog output signal, a reduction in the output resistance and also an increase of the bandwidth of the analog output signal are accomplished because of the fact that any possible value of the digital input signal (B0 . . . B7) connects at least two taps (A0 . . . A257) of the voltage divider chain (W1 . . . W257) together to the output.

Abstract: For determining the half-cycle durations of the input signal which is presented as a sequence of sampled values, its zero crossings are approximated by lines which interconnect the two sampled values of different signs on both sides of the zero crossing. The half-cycle duration is derived from the number of sampled values within a period, i.e. between two consecutive zero crossings, and from the time intervals at the beginning and end of each half-cycle determined by the intersection of the approximation line with the axis. The time intervals at the beginning and end of each period are corrected for a more accurate determination of the duration and the time intervals during which the values of the individual half-cycle durations are stored, are made to approximate to these half-cycle durations. The instantaneous frequency of the input signal is determined from the values of the half-cycle durations which have thus been shifted in time by forming the reciprocal.