Abstract: A selective call receiver for receiving and displaying information in a nationwide communication system includes circuitry to decode and process transmitted channel identification information. The receiver displays channel identification indicia in response to a user interrogation thereby confirming proper operation of the receiver on the system at the expected location.

Abstract: A method of selecting an alert pattern for a pager receiver including calling the pager terminal on a telephone, providing a unit ID, a pattern select coded signal and identifying a new alert pattern. The pager terminal then transmits a "replace alert pattern signal", which prepares a reprogrammable memory in the pager receiver for reprogramming, and the selected new alert pattern, which is then programmed into the alert pattern memory.

Abstract: A digital selective call receiver is modified to enhance the address decoding capability by providing access to received data, bit and frame synchronization signals, and a detect input terminal of an annunciator. A selectively attachable additional independent address decoding device including additional memory and an independent address decoder operating in parallel with the decoder in the selective call receiver is attached to the receiver for accessing the various signals and providing a detect signal to the annunicator when an additional independent address is decoded.

Abstract: A paging receiver includes a nonvolatile memory which is readable for controlling the operation of the paging device and is capable of being partitioned into a plurality of regions. A protect means is also included for allowing modification to a selected region of the nonvolatile memory in response to an unlock signal. In a first embodiment, the unlock signal is externally applied to the paging receiver. In a second embodiment, the unlock signal is generated when a predetermined coded signal stored in the paging receiver matches a received coded signal. In a third embodiment, the protect means further includes a switch means to permit the selected region of memory to be modified while preventing other regions of memory to be modified.

Abstract: An battery powered, adaptive signal decoder is disclosed which is capable of processing detected encoded signals in accordance with a plurality of decoding schemes. The decoder has an equivalent microcomputer implementation. Energy conservation means operating independently of the detected signals acts to conserve the energy of the battery.

Abstract: A radio communication receiver decodes digital signals transmitted over a radio link and is capable of altering the bit rate of the receiver to match the bit rate transmitted form a remote location. The receiver includes a receiver portion 21 receiving radio signals and producing a received signal. A microporocessor 26 is used for decoding the received signal. The microprocessor (26) is responsive to a bit rate signal that is generated by a programmable divider (33). The microprocessor (26) is adpated to detect a predetermined code signal to alter the timing characteristic of the bit rate signal for generating a bit rate signal at a second rate for decoding received signals at a second bit rate designated by the predetermined code signal.

Abstract: A paging system providing an LPC encoded speech output having an adaptive bit rate. The LPC bit rate is adaptively modified based on paging system airtime loading. Synthesizer circuitry in the paging receivers, together with a system signaling scheme is used to update the paging receivers as to the LPC bit rate, allows the paging receiver to decode the adaptive bit rate signal.

Abstract: A gear coupled, counter-rotating vibratory assembly is described for producing a fine tuned accurate linear vibratory motion without any twisting force component. The assembly has two parallel shafts that extend through a gear casing with cantilevered ends extending outward from both sides of casing. Large intermeshing gears are mounted on the shafts to rotate the shafts in counter-rotating synchronized motion. One of the gears has metal teeth and the other gear has plastic teeth. Identical eccentric weights are mounted on the cantilevered shaft ends outside of the gear casing at the same angular positions to generate the linear vibratory motion. The eccentric weights on the drive shaft are offset inward of the weights on the driven shaft. The radius of each of the eccentric weights is greater than the radius of the gear but less than the diameter of the gears.

Abstract: A wrist worn device includes a digital watch circuit and a receiver circuit which responds to coded message signals including selective call signalling and message information. An input steering circuit interfaces between the watch circuit and the receiver circuit for normally providing control of the watch circuit by switches located in the device case. The normal watch functions of the switches are permanently marked on the device case. The watch circuit and the receiver circuit couple to an information selector circuit which normally selects the watch output for a common display. When coded message signals are received, the switches are enabled to control the receiver circuit, and the received message information is selected for display. New indicia, electronically selected by the information selector circuit, are displayed on the display defining the new functions of the switches.

Abstract: A paging receiver with an LPC speech synthesizer is described. The paging receiver of the present invention includes a controller and decoder, and a microprocessor controlled speech synthesizer both coupled to a dual port memory. Digitally encoded voice messages are stored in a dual port memory which includes a scratchpad area for storing control words and address pointers which indicate the attributes and location of stored digitally encoded voice messages. Messages are reconstructed by reading the control words and address pointers and processing the information stored in memory with a speech synthesizer. The structure is adapted to store and process LPC encoded signals and it permits a message to be stored while another is being reproduced. In addition, information contained in the control words permits old or read messages to be discarded if a new message must be stored.

Abstract: A trimmable current source for use with low voltage circuitry includes a plurality of trimming networks. A voltage-divider circuit is connected to the trimming networks. Each of the trimming networks includes a resistor in an isolated epitaxial region series connected to a zener diode. A programming signal, having a voltage level which would normally damage the low voltage circuitry can be applied to the junction of the resistor and zener diode, and to the isolated epitaxial region containing the resistor of the trimming network to be programmed without damage to the low voltage circuitry.

Abstract: In system capable of self turn-off, a circuit arrangement for providing a controlled turn-off includes a detecting circuit for detecting actuation of a turn-off switch, thereby providing a turn-off authorization signal. A turn-off protection circuit is coupled to the detecting circuit and a controller is coupled to the turn-off protect circuit and the detecting circuit. The controller disables the turn-off protect circuit when the turn-off authorization is received and present. The controller generates a turn-off signal for powering the system down after the turn-off protect circuit has been disabled.

Abstract: A trimmable circuit includes a first transistor for generating an output current and a plurality of programmable trimming networks connected to the first transistor for regulating the output current of the first transistor. The plurality of programmable trimming networks include a network for decreasing the output current of the first transistor by introducing a second transistor into the trimmable circuit to draw current away from the first transistor and a network for increasing the output current of the first transistor. The trimmable circuit further includes a voltage-divider circuit connected to the plurality of programmable trimming networks, for limiting the voltage across any trimming network during programming.

Abstract: A paging system providing an LPC encoded speech output having an adaptive bit rate. The LPC bit rate is adaptively modified based on paging system airtime loading. Synthesizer circuitry in the paging receivers, together with a system signalling scheme is used to update the paging receivers as to the LPC bit rate, allows the paging receiver to decode the adaptive bit rate signal.

Abstract: An I.sup.2 L programmable read only memory (PROM) row driver circuit sinks current from a row of memory elements when selectively activated. The circuit operates in the read mode at very low power levels and down to 1.0 volt. The circuit has two current sinking capabilities, a low current capability for the read mode and a high current capability for the program mode. Switching between modes is accomplished merely by changing the voltage on a power supply terminal; 1-3 volts for the read mode and 9-12 volts for program.

Abstract: A logic circuit is provided in a multifunction selective call receiver operating in a time sequential zone batched message communication system to prevent repeated alerts of the same message. A single lockout timer is reset by the first detection of a message function signal, and further alerts for that function are disabled for a time interval which may be extended by additional message function detects corresponding to other functions.

Abstract: An I.sup.2 L programmable read only memory (PROM) output circuit has a selectable dual non-inverting input differential amplifier with each non-inverting input connected to a different column of memory elements. In the read mode the circuit operates at very low power levels and down to 1 volt. To program the memory elements, the circuit includes two selectable programming current sources which self extinguish as soon as the memory element being programmed changes from its unprogrammed to its programmed state. Switching between the read and program modes is accomplished merely by changing the voltage on the B+ terminal; 1-3 volts for read and 9-12 volts for program.

Abstract: A reduced power consumption low battery indicator comprising in the preferred embodiment a transducer driver which drives a transducer to provide an audible alert. A microprocessor is used to generate a squarewave signal to power the transducer driver whenever the battery is depleted to a first predetermined level. A first low battery sensor is used to determine when the battery is depleted to the first predetermined level and generates a signal which is directed to the microprocessor to commence generation of the signal to drive the transducer driver. A second low battery sensor is used to determine when the battery is depleted to a second predetermined level and generates an output signal which is directed to the transducer driver which then drives the transducer at a lower power consumption rate.

Abstract: A power supply circuit includes a battery power source connected by a switch to the input of a DC to DC converter. The output of the DC to DC converter is connected to a filter capacitor and a load. A crow-bar is connected to the input and the output of the DC to DC converter. The crow-bar shorts the output to ground to discharge the capacitor when the voltage at the input drops to a predetermined value.

Abstract: The present invention in the preferred embodiment comprises a plurality of current mirror circuit stages connected together for amplifying a first input signal and generating an output signal. A shunt path circuit is connected to the first stage of the plurality of current mirror stages and when activated by a second input signal shunts a portion of the first input signal to ground, thus reducing the current flow into the plurality of current mirror stages. During normal operation, when the shunt path circuit is inactivated, the last stage of the plurality of current mirror stages functions as a switch and passes all of the amplified first input signal. However, during the low power consumption mode, when the shunt path circuit is activated, the last stage of the plurality of current mirror circuit stages functions as a current mirror circuit and passes current at a considerably reduced level.