Patents by Inventor Wan-Ching Huang

Wan-Ching Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240114545
    Abstract: A method, a wireless modem and a mobile device for wireless communication are provided. The method for wireless communication includes: judging a plurality of service types for a plurality of cells; judging a plurality of gears for each of the service types; obtaining a customization favor setting; obtaining a plurality of weighted priority values for the plurality of cells according to the plurality of service types and the customization favor setting; obtaining a plurality of weighted signal quality values for the plurality of cells according to the plurality of service types, the plurality of gears for each of the plurality of service types and the customization favor setting; in an idle mode, triggering mobility via cell reselection which uses the weighted priority values or the weighted signal quality values; and in a connected mode, triggering mobility via measurement reports which are generated based on the weighted signal quality values.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 4, 2024
    Inventors: Yu-Ting SUN, Wan-Ting HUANG, I-Ching HSIEH
  • Patent number: 9977699
    Abstract: A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: May 22, 2018
    Assignee: MediaTek, Inc.
    Inventors: Jia-Ming Chen, Hung-Lin Chou, Ya-Ting Chang, Shih-Yen Chiu, Chia-Hao Hsu, Yu-Ming Lin, Wan-Ching Huang, Jen-Chieh Yang, Pi-Cheng Hsiao
  • Publication number: 20170160962
    Abstract: A multicore processor system includes multiple processor cores. When a processor core goes offline, the offline processor core is mapped to a mapped processor core, which is selected from an emulated processor core and one or more online processor cores among the multiple processor cores. The emulated processor core is a software construct containing an emulated state of the offline processor core. When the multicore processor system receives a system call that is sent from a requestor to the offline processor core to request for system information from the offline processor core, the system call is re-directed to the mapped processor core. The system information is returned from the mapped processor core to the requestor in response to the system call.
    Type: Application
    Filed: November 29, 2016
    Publication date: June 8, 2017
    Inventors: Shih-Yen Chiu, Wan-Ching Huang, Chung-Ho Chang, Ya-Ting Chang, Ming-Ju Wu, Nicholas Ching Hui Tang
  • Patent number: 9665161
    Abstract: A method and a computer-readable medium for dynamically managing power of a multi-core processor of a computing system are provided. The multi-core processor generates a dynamic voltage and frequency scaling (DVFS) table, determines a first index by alternatively selecting either a power budget or a required performance thereof, determines a current thread level parallelism (TLP) of the computing system, selects one of entries according to the current TLP and the first index, and configure first cores and second cores thereof according to a first settings and a second settings of the selected entry.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: May 30, 2017
    Assignee: MEDIATEK INC.
    Inventors: Jih-Ming Hsu, Wen-Tsan Hsieh, Che-Ming Hsu, Yeh-Ji Chou, Jen-Chieh Yang, Shih-Yen Chiu, Wan-Ching Huang, Ming-Hsien Lee
  • Publication number: 20160154649
    Abstract: A switching method for context migration among a plurality of physical processor cores is provided. Each of the physical processor cores is mapped to a corresponding logical processor core. The switching method includes migrating a processor hardware context from a first physical processor core to a second physical processor core which is different from the first physical processor core. The first physical processor core and the second physical processor core are mapped to a first logical processor core and a second logical processor core which is different from the first logical processor core, respectively prior to the migration. The switching method further includes remapping the first physical processor core to the second logical processor core and remapping the second physical processor core to the first logical processor core.
    Type: Application
    Filed: July 15, 2015
    Publication date: June 2, 2016
    Inventors: Yu-Teng LIN, Wan-Ching HUANG, Yu-Pin LIN, Nicholas Ching Hui TANG
  • Publication number: 20160139964
    Abstract: A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 19, 2016
    Inventors: Jia-Ming CHEN, Hung-Lin CHOU, Ya-Ting CHANG, Shih-Yen CHIU, Chia-Hao HSU, Yu-Ming LIN, Wan-Ching HUANG, Jen-Chieh YANG, Pi-Cheng HSIAO
  • Publication number: 20160062447
    Abstract: A method and a computer-readable medium for dynamically managing power of a multi-core processor of a computing system are provided. The multi-core processor generates a dynamic voltage and frequency scaling (DVFS) table, determines a first index by alternatively selecting either a power budget or a required performance thereof, determines a current thread level parallelism (TLP) of the computing system, selects one of entries according to the current TLP and the first index, and configure first cores and second cores thereof according to a first settings and a second settings of the selected entry.
    Type: Application
    Filed: July 29, 2015
    Publication date: March 3, 2016
    Inventors: Jih-Ming Hsu, Wen-Tsan Hsieh, Che-Ming Hsu, Yeh-Ji Chou, Jen-Chieh Yang, Shih-Yen Chiu, Wan-Ching Huang, Ming-Hsien Lee