Abstract: A noise adaptive automatic gain control circuit (100) includes an automatic gain control amplifier (105) for automatically adjusting the gain of the circuit (100) in response to an input signal applied to the input. A detector (135) is provided for detecting the presence of any background noise that may be present. Further, a voltage generator (126), a comparator (124), and a microcomputer (150) is provided for dynamically adjusting the gain of the AGC amplifier (105) to substantially prevent the amplification of the background noise. In other aspects of the present invention, a voice lull detector (140) detects voice lulls (402) in the input signal applied to the input. Further, a programmable amplifier (120) substantially maintains the gain of the AGC amplifier (105) to a constant level during voice lulls (402) to prevent excessive amplification.

Abstract: A four port antenna switch (300) for switching a receive port (320) and a transmit port (310) between a remote antenna port (330) and a standard antenna port (340) is provided. The switching actions of the receive port (320) between the remote antenna port (330) and the standard antenna port (340) is provided by a relay (350) under the control of a relay controller (352, 354, 400). The switching of the transmit port (310) between the standard antenna port (340) and the remote antenna port (330) is provided by diode switches (360, 370) under the control of diode switch controllers (332, 324, 312, 314, 400). The switching actions of the relay (350) and the diode switches (370, and 360) is complementary to each other, wherein sufficient isolation between the receive port and the transmit port is provided. In this arrangement, a low power relay may be used because the relay only switches low level received signals, and the high power transmit signals are switched by the pins.

Abstract: A synthesizer circuit with spur compensation utilizes fractional division in the synthesizer loop. The fractional divider includes means for compensating the spurs when the fractional numerator N=0. The synthesizer includes means for selecting a reference divisor R such that a non zero value of fractional numerator is produced and such that the generated spurs fall below the side band noise limits of the synthesizer's voltage controlled oscillator.

Abstract: An improved mixed down synthesizer scheme 10 having a first phase locked loop 12 and a second phase locked loop 14 provides a first frequency and a second frequency respectively. The first phase locked loop 12 has at least a first programmably tunable filter 30 and a mixer 28. The second phase locked loop 14 has an output received by the mixer 28 in the first phase locked loop 12. A controlling means (18 and 20) controls the first and second frequencies and tunes the first programmably tunable filter 30. The first and the second phase locked loops 12 and 14 are programmed to maintain a constant frequency ratio between the first and second frequencies in order to maintain a minimum frequency offset from the mixed-in spurious products.